Drift management in a phase change memory and switch (PCMS) memory device
The present disclosure relates to the drift management for a memory device. In at least one embodiment, the memory device of the present disclosure may include a phase change memory and switch (hereinafter “PCMS”) memory cell and a memory controller that is capable of implementing drift management to control drift. Other embodiments are described and claimed.
1. A drift management method comprising:
storing a time when a first memory state is written into a first memory bit in a first memory block of a memory device, the memory device having two or more memory blocks;
before writing a second memory state into a memory bit in the first memory block after a time lapse since the first memory state is written, comparing the time lapse with a preset time; and
writing the second memory state into a memory bit in a memory block different from the first memory block if the time lapse is equal to or greater than the preset time.
2. The method of claim 1 , further comprising writing the second memory state into a memory bit in the first memory block if the time lapse is less than the preset time.
3. The method of claim 2 , further comprising storing the second memory state in a buffer before writing the second memory state into a memory bit.
4. The method of claim 1 , further comprising transferring the first memory state in the first memory bit into a memory bit in a memory block different from the first memory block if the time lapse is equal to or greater than the preset time.
5. The method of claim 1 , wherein the first memory state is a SET state and the second memory state is a RESET state.
6. The method of claim 1 , wherein the first memory state is a RESET state and the second memory state is a SET state.
7. The method of claim 1 , wherein storing a time when a first memory state is written into a first memory bit of a memory device comprises storing a time when a SET or a RESET state is written into a first memory bit of a phase change memory and switch (PCMS) memory device.
8. The method of claim 1 , wherein the memory device comprises a non-volatile memory.
9. A memory device, comprising:
a phase change memory and switch (PCMS) memory cell; and
a memory controller that is capable of implementing drift management to control drift of the PCMS memory cell wherein the memory controller is configured to determine whether to implement the drift management based on a comparison of a preset time with a lapse of time since a first memory state is written into a first memory bit, wherein, to control drift of the PCMS memory cell, the memory controller is configured to:
store a time when the first memory state is written into the first memory bit in a first memory block of the memory device, the memory device having two or more memory blocks;
before writing a second memory state into a memory bit in the first memory block after the time lapse since the first memory state is written, compare the time lapse with the preset time;
write the second memory state into a memory bit in a memory block different from the first memory block if the time lapse is equal to or greater than the preset time; and
write the second memory state into a memory bit in the first memory block if the time lapse is less than the preset time.
10. The memory device of claim 9 , wherein the PCMS memory cell comprises a chalcogenide material, an Ovonic material, or combinations thereof.
11. The memory device of claim 9 , wherein the memory device comprises a non-volatile memory.
12. The memory device of claim 9 , wherein said memory controller is further configured to store the second memory state in a buffer before writing the second memory state into a memory bit.
13. The memory device of claim 9 , wherein said memory controller is further configured to transfer the first memory state in the first memory bit into a memory bit in a memory block different from the first memory block if the time lapse is equal to or greater than the preset time.
14. A system, comprising:
a processor; and
a memory device coupled to the processor, the memory device comprising a phase change memory and switch (PCMS) memory cell and a memory controller that is configured to determine whether to control drift of the phase change memory and switch (PCMS) memory cell based on a time lapse since a first memory state was written into a first memory bit, wherein said memory controller is configured to:
store a time when the first memory state is written into the first memory bit in a first memory block of the memory device, the memory device having two or more memory blocks;
before writing a second memory state into a memory bit in the first memory block after the time lapse since the first memory state is written, compare the time lapse with a preset time;
write the second memory state into a memory bit in a memory block different from the first memory block if the time lapse is equal to or greater than the preset time; and
write the second memory state into a memory bit in the first memory block if the time lapse is less than the preset time.
15. The system of claim 14 , wherein the processor comprises a microprocessor, a digital signal processor, an application-specific integrated circuit, a microcontroller, or combinations thereof.
16. The system of claim 14 , further comprising an input/output device and a wireless interface coupled to the processor.
17. The system of claim 14 , wherein the PCMS memory cell comprises a chalcogenide material, an Ovonic material, or combinations thereof.
18. The system of claim 14 , wherein the memory device comprises a non-volatile memory.