Optimizing gate profile for performance and gate fill

1. A semiconductor device, comprising:

a semiconductor substrate;

an isolation structure above the semiconductor substrate, the isolation structure having a top surface;

a fin extending above the semiconductor substrate and above the isolation structure, the fin comprising a source region and drain region located on opposite sides of a channel region, and the channel region of the fin comprising a topmost surface;

a gate stack over the channel region of the fin and over a portion of the isolation structure, wherein the gate stack has a lateral width on a top of the fin less than a lateral width of the gate stack at a top of the gate stack, the gate stack comprising a top portion, a tapered portion and a bottom portion wherein the top portion is separated from the bottom portion by the tapered portion, wherein the top portion and an entirety of the tapered portion and a portion of the bottom portion are above the topmost surface of the channel region of the fin, and wherein a width of the top portion is greater than a width of the bottom portion, wherein the top portion has a lateral width near a center region of the top portion less than a lateral width near a top region of the top portion and less than a lateral width of a bottom region of the top portion, wherein the bottom portion has substantially vertical sidewalls along a direction normal to the top surface of the isolation structure, wherein the top portion has a vertical length greater than a vertical length of the bottom portion, and wherein the bottom portion extends from the top surface of the isolation structure to the tapered portion by a first distance and extends from the topmost surface of the channel region of the fin to the tapered portion by a second distance, the second distance less than the first distance, and wherein the gate stack comprises a gate dielectric along sidewalls of the top portion, the tapered portion and the bottom portion of the gate stack.

2. The semiconductor device of claim 1 , wherein the width of the top portion is at least two times greater than the width of the bottom portion.

3. The semiconductor device of claim 2 , wherein the width of the top portion is 40 nm and the width of the bottom portion is 20 nm.

4. The semiconductor device of claim 1 , wherein the vertical length of the bottom portion is greater than the height of the fin.

5. The semiconductor device of claim 1 , wherein the top of the tapered portion is at the midpoint of the gate stack height.

6. The semiconductor device of claim 1 , wherein the tapered portion comprises curved sidewalls.

7. The semiconductor device of claim 6 , wherein the curved sidewalls are concave in profile.

8. The semiconductor device of claim 1 , wherein a ratio of gate height to gate length is greater than 5 to 1.

9. The semiconductor device of claim 8 , wherein the ratio of gate height to gate length is 10 to 1.

10. The semiconductor device of claim 1 , wherein the tapered portion is disposed below the midpoint of the gate height and above the fin.

11. The semiconductor device of claim 1 , wherein the widths of the top and bottom portions are constant across the entire height of each respective portion.

12. A computing device, comprising:

a motherboard;

a processor mounted on the motherboard; and

a communication chip fabricated on the same chip as the processor or mounted on the motherboard;

wherein the processor comprises a semiconductor device comprising:

a semiconductor substrate;

an isolation structure above the semiconductor substrate, the isolation structure having a top surface;

a fin extending above the semiconductor substrate and above the isolation structure, the fin comprising a pair of source and drain regions disposed on opposite sides of a channel region, and the channel region of the fin comprising a topmost surface;

a gate stack over the channel region of the fin and over a portion of the isolation structure, wherein the gate stack has a lateral width on a top of the fin less than a lateral width of the gate stack at a top of the gate stack, the gate stack comprising a top portion, a tapered portion and a bottom portion wherein the top portion is separated from the bottom portion by the tapered portion, wherein the top portion and an entirety of the tapered portion and a portion of the bottom portion are above the topmost surface of the channel region of the fin, and wherein a width of the top portion is greater than a width of the bottom portion, wherein the top portion has a lateral width near a center region of the top portion less than a lateral width near a top region of the top portion and less than a lateral width of a bottom region of the top portion, wherein the bottom portion has substantially vertical sidewalls along a direction normal to the top surface of the isolation structure, wherein the top portion has a vertical length greater than a vertical length of the bottom portion, and wherein the bottom portion extends from the top surface of the isolation structure to the tapered portion by a first distance and extends from the topmost surface of the channel region of the fin to the tapered portion by a second distance, the second distance less than the first distance, and wherein the gate stack comprises a gate dielectric along sidewalls of the top portion, the tapered portion and the bottom portion of the gate stack.

13. The semiconductor device of claim 12 , wherein the width of the top portion is at least two times greater than the width of the bottom portion.

14. The semiconductor device of claim 12 , wherein the tapered portion comprises curved sidewalls.

15. The semiconductor device of claim 12 , wherein the curved sidewalls are concave in profile.

16. The semiconductor device of claim 12 , wherein a ratio of gate height to gate length is greater than 5 to 1.

17. The semiconductor device of claim 12 , wherein the tapered portion is disposed below the midpoint of the gate height and above the fin.