Method and system for platform management messages across peripheral component interconnect express (PCIe) segments

1. A method to manage platform management messages comprising:

receiving a serial differential, point-to-point interconnect management message as a media-independent protocol packet, wherein the media-independent protocol packet utilizes a Management Component Transport Protocol (MCTP) over Peripheral Component Interconnect (PCI) Express (PCIe) packet format allowing an extension of the serial, differential, point-to-point interconnect;

extracting a bus segment identifier and an endpoint identifier from distinct portions of a destination endpoint identifier field of the packet having the MCTP over PCIe packet format; and

routing the received management message using the bus segment identifier and the endpoint identifier, including routing the received management message to a bus segment uniquely identified by the bus segment identifier, including using a local segment identifier register to select between use of the endpoint identifier or target bus identifier field bits in order to lookup a target identifier with a MCTP source address decoder.

2. The method of claim 1 , further comprising determining whether to interpret the portion of a destination field of the format allowing an extension of the serial, differential, point-to-point interconnect of the received serial differential, point-to-point interconnect management message as a bus segment identifier by checking a setting within a basic input/out system (BIOS) of the computing system.

3. The method of claim 2 , wherein the BIOS of the computing system specifies a number of bits within the destination field of the format allowing an extension of the serial, differential, point-to-point interconnect of the received serial differential, point-to-point interconnect management message is to be interpreted as a serial differential, point-to-point interconnect bus segment identifier.

4. The method of claim 2 , wherein the setting within the BIOS indicates whether to interpret the portion of destination field of the format allowing an extension of the serial, differential, point-to-point interconnect of the received serial differential, point-to-point interconnect management message as a serial differential, point-to-point interconnect bus segment identifier or to interpret a portion of a target identifier field of the format allowing an extension of the serial, differential, point-to-point interconnect as a processor node identifier.

5. The method of claim 4 , wherein the setting within the BIOS of the computing system indicates that the portion of a target identifier field of the format allowing an extension of the serial, differential, point-to-point interconnect of the received serial differential, point-to-point interconnect management message being interpreted as a processor node identifier, wherein the serial differential, point-to-point interconnect management message is routed to the identified processor node, and wherein the identified processor node is coupled with a first processor from which the serial differential, point-to-point interconnect message is received through a point-to-point processor interconnect.

6. The method of claim 2 , furthering comprising determining a number of bits within the destination field of the format allowing an extension of the serial, differential, point-to-point interconnect of the received serial differential, point-to-point interconnect management message is to be interpreted as a serial differential, point-to-point interconnect bus segment identifier prior to extracting the serial differential, point-to-point interconnect bus segment identifier when the portion of destination field of the format allowing an extension of the serial, differential, point-to-point interconnect is determined to be interpreted as the serial differential, point-to-point interconnect bus segment identifier.

7. The method of claim 1 , wherein the portion of destination field of the format allowing an extension of the serial, differential, point-to-point interconnect is to be interpreted as a serial differential, point-to-point interconnect bus segment identifier is one of one bit, two bits, three bits, four bits, and five bits.

8. The method of claim 1 , wherein routing the serial differential, point-to-point interconnect management message comprises comparing the serial differential, point-to-point interconnect bus segment identifier within the portion of destination field of the format allowing an extension of the serial, differential, point-to-point interconnect with a register of the root complex containing a segment identifier associated with a first processor.

9. The method of claim 8 , wherein the serial differential, point-to-point interconnect management message contains the serial differential, point-to-point interconnect bus segment identifier being inserted by a second processor of the computing system.

10. The method of claim 9 , wherein the second processor of the computing system further contain a serial differential, point-to-point interconnect bus segment identifier inserted in a source field.

11. An apparatus, comprising:

a root complex, the root complex including:

message logic configured to receive a serial differential, point-to-point interconnect management message, the serial differential, point-to-point interconnect management message to be transmitted as a media-independent protocol packet, wherein the media-independent protocol packet is to utilize a Management Component Transport Protocol (MCTP) over Peripheral Component Interconnect (PCI) Express (PCIe) packet format allowing an extension of the serial, differential, point-to-point interconnect;

decoder logic configured to determine whether to interpret a portion of an endpoint destination field of the packet having the MCTP over PCIe packet format allowing an extension of the serial, differential, point-to-point interconnect of the serial differential, point-to-point interconnect management message that is to be received as a serial differential, point-to-point interconnect bus segment identifier;

extraction logic configured to extract the serial differential, point-to-point interconnect bus segment identifier and an endpoint identifier from distinct portions of the destination field of the packet having the MCTP over PCIe packet format when a portion of destination field of the format allowing an extension of the serial, differential, point-to-point interconnect is determined to be interpreted as a serial differential, point-to-point interconnect bus segment identifier; and

management logic configured to route the received serial differential, point-to-point interconnect management message, using the point-to-point interconnect bus segment identifier and the endpoint identifier, to a serial differential, point-to-point interconnect bus segment to be uniquely specified by the serial differential, point-to-point interconnect bus segment identifier within the portion of destination field of the format allowing an extension of the serial, differential, point-to-point interconnect, the management logic including a local segment identifier register to select between use of the endpoint identifier or target bus identifier field bits in order to lookup a target identifier with a MCTP source address decoder.

12. The apparatus of claim 11 , wherein the computing system further includes a basic input/out system (BIOS) configured to store a setting for the computing system to determine whether to interpret the portion of destination field of the format allowing an extension of the serial, differential, point-to-point interconnect of the received serial differential, point-to-point interconnect management message being a serial differential, point-to-point interconnect bus segment identifier.

13. The apparatus of claim 12 , wherein the BIOS of the computing system specifies a number of bits within the destination field of the format allowing an extension of the serial, differential, point-to-point interconnect of the received serial differential, point-to-point interconnect management message is to be interpreted as a serial differential, point-to-point interconnect bus segment identifier.

14. The apparatus of claim 12 , wherein the setting within the BIOS indicates whether to interpret the portion of destination field of the format allowing an extension of the serial, differential, point-to-point interconnect of the received serial differential, point-to-point interconnect management message as a serial differential, point-to-point interconnect bus segment identifier or to interpret a portion of a target identifier field of the format allowing an extension of the serial, differential, point-to-point interconnect of the received serial differential, point-to-point interconnect management message as a processor node identifier.

15. The apparatus of claim 14 , wherein the setting within the BIOS of the computing system indicates that the portion of a target identifier field of the format allowing an extension of the serial, differential, point-to-point interconnect of the received serial differential, point-to-point interconnect management message being interpreted as a processor node identifier, wherein the serial differential, point-to-point interconnect management message is routed to the identified processor node, and wherein the identified processor node is coupled with a first processor from which the serial differential, point-to-point interconnect message is received through a point-to-point processor interconnect.

16. The apparatus of claim 11 , wherein the packet interpretation logic further configured to determine a number of bits within the destination field of the format allowing an extension of the serial, differential, point-to-point interconnect of the received serial differential, point-to-point interconnect management message is to be interpreted as a serial differential, point-to-point interconnect bus segment identifier prior to extracting the serial differential, point-to-point interconnect bus segment identifier when the portion of destination field is determined to be interpreted as the serial differential, point-to-point interconnect bus segment identifier.

17. The apparatus of claim 11 , wherein the portion of destination field of the format allowing an extension of the serial, differential, point-to-point interconnect of the received serial differential, point-to-point interconnect management message is to be interpreted as a serial differential, point-to-point interconnect bus segment identifier is one of one bit, two bits, three bits, four bits, and five bits.

18. The apparatus of claim 11 , wherein the root complex further comprises a local segment identifier register configured to store a segment identifier of a local serial differential, point-to-point interconnect bus segment of a first processor, and wherein the stored segment identifier of the local serial differential, point-to-point interconnect bus segment is utilized to compare with an extracted serial differential, point-to-point interconnect bus segment identifier of a received media-independent protocol message.

19. The apparatus of claim 18 , further comprising a second processor, wherein the second processor is configured to insert a serial differential, point-to-point interconnect bus segment identifier into a media-independent protocol message to be transmitted.

20. The apparatus of claim 19 , wherein the second processor is further configured to insert the serial differential, point-to-point interconnect bus segment identifier in a source field of the media-independent protocol message to be transmitted.

21. The apparatus of claim 11 , further comprising:

an endpoint coupled to the root complex, the endpoint to:

receive a serial differential, point-to-point interconnect management message, the serial differential, point-to-point interconnect management message to be transmitted as a media-independent protocol packet, wherein the media-independent protocol packet is to utilize a format allowing an extension of the serial, differential, point-to-point interconnect;

determine whether to interpret a portion of destination field of the format allowing an extension of the serial, differential, point-to-point interconnect of the serial differential, point-to-point interconnect management message that is to be received as a serial differential, point-to-point interconnect bus segment identifier;

extract the serial differential, point-to-point interconnect bus segment identifier and an endpoint identifier from distinct portions of the destination field when a portion of destination field of the format allowing an extension of the serial, differential, point-to-point interconnect is determined to be interpreted as a serial differential, point-to-point interconnect bus segment identifier; and

route the received serial differential, point-to-point interconnect management message, using the point-to-point interconnect bus segment identifier and the endpoint identifier, to a serial differential, point-to-point interconnect bus segment to be uniquely specified by the serial differential, point-to-point interconnect bus segment identifier within the portion of destination EID field of the format allowing an extension of the serial, differential, point-to-point interconnect.

22. The apparatus of claim 11 , further comprising:

a touch enabled input device.

23. An apparatus, comprising:

a root complex, the root complex including:

an management component transport protocol (MCTP) message logic configured to receive a peripheral component interconnect express (PCIe) management message, the PCIe management message being transmitted as a MCTP packet, wherein the MCTP packet utilizes a Management Component Transport Protocol (MCTP) over Peripheral Component Interconnect (PCI) Express (PCIe) packet format allowing an extension of the serial, differential, point-to-point interconnect;

a local segment identifier register to select between use of the endpoint identifier or target bus identifier field bits

a source address decoder logic configured to determine whether to interpret a portion of destination field of the format allowing an extension of the serial, differential, point-to-point interconnect of the received PCIe management message as a PCIe bus segment identifier, the source address decoder logic operable to perform a target identifier lookup based on a selection by the local segment identifier register;

an MCTP packet segmentation identifier extraction logic configured to extract the PCIe bus segment identifier when a portion of an endpoint destination field of the MCTP over PCIe packet format allowing an extension of the serial, differential, point-to-point interconnect is determined to be interpreted as a PCIe bus segment identifier; and

an MCTP over PCIe management logic configured to route the received PCIe management message to a PCIe bus segment specified by the PCIe bus segment identifier within the portion of destination field of the format allowing an extension of the serial, differential, point-to-point interconnect.

24. The apparatus of claim 23 , wherein the computing system further includes a basic input/out system (BIOS) configured to store a setting for the computing system to determine whether to interpret the portion of destination field of the format allowing an extension of the serial, differential, point-to-point interconnect of the received PCIe management message being a PCIe bus segment identifier.

25. The apparatus of claim 23 , wherein the packet interpretation logic further configured to determine a number of bits within the destination field of the format allowing an extension of the serial, differential, point-to-point interconnect of the received PCIe management message is to be interpreted as a PCIe bus segment identifier prior to extracting the PCIe bus segment identifier when the portion of destination field is determined to be interpreted as the PCIe bus segment identifier.