Dynamic sleep for a display panel

1. A display controller, comprising logic to:

detect a frame update when the display controller is in a dynamic sleep state;

wake up from the dynamic sleep state and enter a selective update state at a programmed vertical blanking interrupt (VBI) that precedes an actual VBI;

perform a scan-out with a display panel during the selective update state; and

return to the dynamic sleep state in a same time frame after the scan-out is completed,

wherein the display controller excludes timing logic to send a VBI at every time frame to the display panel to maintain time synchronization between the display controller and the display panel.

2. The display controller of claim 1 , wherein the timing logic to send the VBI at every time frame to the display panel that is excluded from the display controller is associated with a separate power domain with an always-on power rail that is accessible to the display controller.

3. The display controller of claim 1 , wherein the display controller and a central processing unit (CPU) coupled to the display controller enter a reduced power consumption package (PKG) CPU state (C-state) when the display controller is in the dynamic sleep state.

4. The display controller of claim 3 , wherein the reduced power consumption PKG C-state is achieved when all power rails are turned off except an always-on power rail that includes the timing logic to send the VBI at every time frame to the display panel, thereby enabling the display controller and the CPU to enter the reduced power consumption PKG C-state during the dynamic sleep state while the time synchronization between the display controller and the display panel is separately maintained using the always-on power rail.

5. The display controller of claim 1 , further comprising logic to:

start performing the scan-out after the actual VBI when the display panel operates in a synchronous mode or at the actual VBI when the display panel operates in an asynchronous mode; and

complete the scan-out after the actual VBI.

6. The display controller of claim 1 , wherein the programmed VBI that is earlier in time than the actual VBI is determined based on a calculated hardware latency and software latency.

7. The display controller of claim 1 , further comprising logic to:

start performing the scan-out immediately after detection of the frame update and prior to the actual VBI; and

complete the scan-out prior to the actual VBI.

8. The display controller of claim 1 , wherein the logic to perform the scan-out during the selective update state further comprises logic to:

fetch a new frame;

identify changed scanlines of the new frame; and

send the changed scanlines of the new frame to the display panel.

9. The display controller of claim 1 , wherein the display controller is coupled to a display accelerator that drives the display panel.

10. The display controller of claim 1 , wherein the display controller is configured for the dynamic sleep state using one or more of: an embedded DisplayPort (eDP) protocol, a Mobile Industry Processor Interface (MIPI) protocol or a transport agnostic display (TAD) protocol.

11. A display system, comprising:

a display panel;

a display controller coupled to the display panel; and

a central processing unit (CPU) coupled to the display controller, wherein the CPU is associated with an always-on power rail;

wherein the display controller comprises logic to:

detect a frame update when the display controller is in a dynamic sleep state;

wake up from the dynamic sleep state and enter a selective update state at a programmed vertical blanking interrupt (VBI) that is earlier in time than an actual VBI;

perform a scan-out with the display panel during the selective update state; and

return to the dynamic sleep state in a same time frame after the scan-out is completed,

wherein timing logic to send the VBI at every time frame to the display panel to maintain time synchronization between the display controller and the display panel is included in the always-on power rail.

12. The display system of claim 11 , wherein the timing logic to send the VBI at every time frame to the display panel to maintain time synchronization between the display controller and the display panel is excluded from the display controller and is associated with a separate power domain with the always-on power rail that is accessible to the display controller.

13. The display system of claim 11 , wherein the display controller and the CPU enter a reduced power consumption PKG CPU state (C-state) when the display controller is in the dynamic sleep state.

14. The display system of claim 13 , wherein the reduced power consumption PKG C-state is achieved when all power rails are turned off except the always-on power rail that includes the timing logic to send the VBI at every time frame to the display panel, thereby enabling the display controller and the CPU to enter the reduced power consumption PKG C-state during the dynamic sleep state while the time synchronization between the display controller and the display panel is separately maintained using the always-on power rail.

15. The display system of claim 11 , wherein the display controller further comprises logic to:

start performing the scan-out after the actual VBI when the display panel operates in a synchronous mode or at the actual VBI when the display panel operates in an asynchronous mode; and

complete the scan-out after the actual VBI.

16. The display system of claim 11 , wherein the programmed VBI that is earlier in time than the actual VBI is determined based on a calculated hardware latency and software latency.

17. The display system of claim 11 , wherein the display controller further comprises logic to:

start performing the scan-out immediately after detection of the frame update and prior to the actual VBI; and

complete the scan-out prior to the actual VBI.

18. The display system of claim 11 , wherein the logic in the display controller to perform the scan-out during the selective update state further comprises logic to:

fetch a new frame;

identify changed scanlines of the new frame; and

send the changed scanlines of the new frame to the display panel.

19. The display system of claim 11 , further comprising a display accelerator that is positioned in between the display controller and the display panel.

20. The display system of claim 11 , wherein the display controller is configured for the dynamic sleep state using one or more of: an embedded DisplayPort (eDP) protocol, a Mobile Industry Processor Interface (MIPI) protocol or a transport agnostic display (TAD) protocol.

21. A method of making a display system, the method comprising:

providing a display controller that excludes timing logic to send a vertical blanking interrupt (VBI) at every time frame to a display panel to maintain time synchronization between the display controller and the display panel;

coupling the display controller to the display panel;

coupling the display controller to a central processing unit (CPU); and

configuring the display controller with logic to:

detect a frame update when the display controller is in a dynamic sleep state;

wake up from the dynamic sleep state and enter a selective update state at a programmed VBI that is earlier in time than an actual VBI;

perform a scan-out with the display panel during the selective update state; and

return to the dynamic sleep state in a same time frame after the scan-out is completed.

22. The method of claim 21 , further comprising configuring the CPU to be associated with an always-on power rail that includes timing logic to send the VBI at every time frame to the display panel, wherein the timing logic is associated with a separate power domain with the always-on power rail that is accessible to the display controller.

23. The method of claim 21 , further comprising configuring the display controller and the CPU to enter a reduced power consumption package (PKG) CPU state (C-state) when the display controller is in the dynamic sleep state.

24. The method of claim 23 , wherein the reduced power consumption PKG C-state is achieved when all power rails are turned off except an always-on power rail that includes the timing logic to send the VBI at every time frame to the display panel, thereby enabling the display controller and the CPU to enter the reduced power consumption PKG C-state during the dynamic sleep state while the time synchronization between the display controller and the display panel is separately maintained using the always-on power rail.

25. The method of claim 21 , wherein the programmed VBI that is earlier in time than the actual VBI is determined based on a calculated hardware latency and software latency.

26. The method of claim 21 , further comprising coupling a display accelerator to the display controller to drive the display panel.

27. The method of claim 21 , wherein the display controller is configured for the dynamic sleep state using one or more of: an embedded DisplayPort (eDP) protocol, a Mobile Industry Processor Interface (MIPI) protocol or a transport agnostic display (TAD) protocol.