Underfill material flow control for reduced die-to-die spacing in semiconductor packages
View Patent ↗Underfill material flow control for reduced die-to-die spacing in semiconductor packages and the resulting semiconductor packages are described. In an example, a semiconductor apparatus includes first and second semiconductor dies, each having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a common semiconductor package substrate by a plurality of conductive contacts, the first and second semiconductor dies separated by a spacing. A barrier structure is disposed between the first semiconductor die and the common semiconductor package substrate and at least partially underneath the first semiconductor die. An underfill material layer is in contact with the second semiconductor die and with the barrier structure, but not in contact with the first semiconductor die.
1. A semiconductor apparatus, comprising:
first and second semiconductor dies, each having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a common semiconductor package substrate by a plurality of conductive contacts, the first and second semiconductor dies laterally adjacent to one another and separated by a spacing;
a barrier structure disposed between the first semiconductor die and the common semiconductor package substrate and at least partially underneath the first semiconductor die; and
an underfill material layer in contact with the second semiconductor die and with the barrier structure, but not in contact with the first semiconductor die, wherein the underfill material layer is disposed on and over an uppermost surface of the barrier structure at a location of a highest point of the uppermost surface of the barrier structure above the common semiconductor package substrate but is not on a portion of the uppermost surface of the barrier structure underneath the first semiconductor die.
2. The semiconductor apparatus of claim 1 , wherein the barrier structure comprises a plurality of copper traces disposed on an uppermost surface of the common semiconductor package substrate.
3. The semiconductor apparatus of claim 2 , wherein the plurality of copper traces comprises a chevron pattern.
4. The semiconductor apparatus of claim 1 , wherein the barrier structure comprises a patterned ink structure disposed on an uppermost surface of the common semiconductor package substrate.
5. The semiconductor apparatus of claim 1 , wherein the spacing separating the first and second semiconductor dies is approximately 100 microns.
6. The semiconductor apparatus of claim 1 , wherein the first semiconductor die is a memory die, and the second semiconductor die is one selected from a microprocessor die and a system-on-chip (SoC) die.
7. The semiconductor apparatus of claim 1 , wherein the barrier structure comprises a plurality of slots to restrict flow of an underfill material used to form the underfill material layer.
8. The semiconductor apparatus of claim 1 , wherein the first and second semiconductor dies are electrically coupled to one another by an embedded interconnection bridge (EmIB) disposed within the common semiconductor package substrate.
9. The semiconductor apparatus of claim 1 , wherein the barrier structure comprises a plurality of runaway traces for excess portions of the underfill material layer.