IP Library Granted Patent US 9,984,922
Granted Patent B2
US 9,984,922 · App. 15/254,840 · Granted May 29, 2018

Interconnects having sealing structures to enable selective metal capping layers

Inventors: Jun He (Phoenix, AZ); Kevin J. Fischer (Hillsboro, OR); Ying Zhou (Tigard, OR); Peter K. Moon (Portland, OR)
Assignee: Intel Corporation
H01L21/76849H01L21/0217H01L21/02252H01L21/32053H01L21/76802H01L21/76834H01L21/76844H01L21/76856H01L21/76865H01L21/76877H01L21/76888H01L23/5283H01L23/5329H01L23/53209H01L23/53228H01L23/53238H01L23/53266H01L2924/0002
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Quick Facts
Patent No.
US 9,984,922
App. No.
15/254,840
Granted
May 29, 2018
Kind
B2
Abstract

Methods of fabricating a capped interconnect for a microelectronic device which includes a sealing feature for any gaps between a capping layer and an interconnect and structures formed therefrom. The sealing features improve encapsulation of the interconnect, which substantially reduces or prevents electromigration and/or diffusion of conductive material from the capped interconnect.

Claims (30)

1. An interconnect structure comprising:

an interconnect including a conductive material extending into a dielectric material layer;

a barrier layer located between the dielectric material layer and the interconnect conductive material;

a capping layer to cap a first portion of a surface of the interconnect conductive material; and

a structure including a silicon nitride layer adapted to cover the capping layer and to cover a second portion of the surface of the interconnect conductive material by extending into the interconnect conductive material between the capping layer and the dielectric layer.

2. The interconnect structure of claim 1 , wherein the second portion of the surface including at least gap of the interconnect conductive material is not capped by the capping layer.

3. The interconnect structure of claim 1 , wherein the silicon nitride layer that is adapted to cover the second portion of the surface is formed in the interconnect proximate at least one gap exposing the interconnect.

4. The interconnect structure of claim 1 , wherein the silicon nitride layer that is adapted to cover the capping layer covers an upper surface and sidewalls of the capping layer.

5. The interconnect structure of claim 1 , wherein the interconnect conductive material comprises a copper-containing material.

6. The interconnect structure of claim 1 , wherein the capping layer comprises at least one of a refractory metal layer and a refractory metal alloy layer.

7. The interconnect structure of claim 1 , wherein the structure includes a first salicide layer and a second silicide layer.

8. A capped interconnect comprising:

a dielectric material layer having an opening;

a barrier layer disposed on a lower surface and sidewalls of the opening of the dielectric layer;

an interconnect including a conductive material extending into the opening of the dielectric material layer;

a capping layer to cap a first portion of a surface of the interconnect conductive material; and

a structure including a silicon nitride layer adapted to cover the capping layer and to cover a second portion of the surface of the interconnect conductive material by extending into the interconnect conductive material between the capping layer and the dielectric layer.

9. The capped interconnect of claim 8 , wherein the silicon nitride layer that is adapted to cover the second portion of the surface is formed in the interconnect proximate at least one gap exposing the interconnect.

10. The interconnect structure of claim 8 , wherein the silicon nitride layer that is adapted to cover the capping layer covers an upper surface and sidewalls of the capping layer.

11. An integrated circuit structure, comprising:

a dielectric layer comprising silicon, carbon and oxygen;

a first conductive material in the dielectric layer, the first conductive material comprising copper and having an upper surface substantially co-planar with an upper surface of the dielectric layer;

a second conductive material partially surrounding the first conductive material, the second conductive material comprising tantalum and having an upper surface substantially co-planar with the upper surface of the dielectric layer and the upper surface of the first conductive material;

a third conductive material on the upper surface of the first conductive material, the third conductive material comprising cobalt, the third conductive material having a width less than a width of the first conductive material at a location where the first conductive material and the third conductive material meet; and

a sealing layer on the upper surface of the dielectric layer, on a portion of the upper surface of the first conductive material, on the upper surface of the second conductive material, and on the third conductive material, the sealing layer comprising nitrogen and carbon.

12. The integrated circuit structure of claim 11 , wherein the third conductive material is cobalt.

13. The integrated circuit structure of claim 11 , wherein the third conductive material is a cobalt alloy.

14. The integrated circuit structure of claim 11 , wherein the first conductive material is copper.

15. The integrated circuit structure of claim 11 , wherein the second conductive material is tantalum.

16. The integrated circuit structure of claim 11 , wherein the second conductive material is tantalum nitride.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 15, 2022
From: INTEL CORPORATION
To: TAHOE RESEARCH, LTD.
Reel/Frame 061175/0176 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 8, 2016
From: HE, JUN; FISCHER, KEVIN J.; ZHOU, YING; MOON, PETER K.
To: INTEL CORPORATION
Reel/Frame 039679/0538 →
Continuity (5)
Division 14569342 · Dec 12, 2014
Division 13242988 · Sep 23, 2011
Division 12079683 · Mar 28, 2008
Division 11144576 · Jun 3, 2005
Related Publication 20160372366A1 · Dec 22, 2016