Semiconductor devices having ruthenium phosphorus thin films
Embodiments of the present disclosure describe semiconductor devices with ruthenium phosphorus thin films and further describe the processes to deposit the thin films. The thin films may be deposited in a gate stack of a transistor device or in an interconnect structure. The processes to deposit the films may include chemical vapor deposition and may include ruthenium precursors. The precursors may contain phosphorus. A co-reactant may be used during deposition. A co-reactant may include a phosphorus based compound. A gate material may be deposited on the film in a gate stack. The ruthenium phosphorus film may be a metal diffusion barrier and an adhesion layer, and the film may be a work function metal for some embodiments. Other embodiments may be described and/or claimed.
1. A semiconductor device, comprising:
one or more transistors with a gate having a gate stack including
a fin including a semiconductor substrate material,
a high-kappa dielectric material layer adjacent to and in contact with the fin,
a ruthenium-phosphorus (Ru—P) thin film adjacent to and conformally in contact with the high-kappa dielectric material layer, and
a single layer of gate material adjacent to and in contact with the Ru—P thin film, wherein the Ru—P thin film is to function as a diffusion barrier, a nucleation layer, a conductive liner, and an adhesion layer; and
electrical circuitry coupled to the one or more transistors.
2. The semiconductor device of claim 1 , wherein the one or more transistors are one or more tri-gate transistors, and the semiconductor substrate is a fin of the tri-gate transistor.
3. The semiconductor device of claim 1 , wherein the semiconductor substrate is composed of silicon, silicon germanium, or germanium.
4. The semiconductor device of claim 1 , wherein the Ru—P thin film is approximately 1 to 5 nanometers thick.
5. The semiconductor device of claim 1 , wherein the Ru—P thin film is deposited by a chemical vapor deposition (CVD) process, wherein the CVD process includes: placing the semiconductor device in a vacuum chamber, heating the semiconductor device at a temperature of approximately 200 to 450 degrees Celsius, depositing a ruthenium precursor on the high-kappa dielectric material layer, and curing the ruthenium precursor to form the Ru—P thin film.
6. The semiconductor device of claim 5 , wherein the precursor includes Ru(PF 3 ) 4 H 2 , cis-H 2 Ru(P(CH 3 ) 3 ) 4 , R 2 PCH 2 CH 2 PR 2 , R 2 PCH 2 CH 2 NHCH 2 CH 2 PR 2 , a bidentate ligand containing phosphorus, a tridentate ligand containing phosphorus, bis(cyclopentadienyl) ruthenium, a ruthenium amidinate complex, a ruthenium diazadiene complex, a ruthenium carbonyl complex, or bis(R-cyclopentadienyl) ruthenium, and wherein R is methyl, ethyl, propyl, isopropyl, or t-butyl.
7. The semiconductor device of claim 6 , wherein the depositing of the ruthenium precursor includes co-flow of a co-reactant, wherein the co-reactant includes hydrogen (H 2 ), ammonia (NH 3 ), phosphine (PH 3 ), monoalkylphosphine (H 2 PR), dialkylphosphine (HPRR′), or trialkylphosphine (PRR′R″), or a substituted or unsubstituted hydrazine, wherein R, R′ and R″ are methyl, ethyl, propyl, isopropyl, or t-butyl.
8. The semiconductor device of claim 6 , wherein the depositing of the ruthenium precursor includes plasma enhanced CVD and co-flow of co-reactant ammonia.
9. The semiconductor device of claim 1 , further comprising:
a liner disposed between and coupled to the high-kappa dielectric material layer and the Ru—P thin film.
10. A semiconductor device, comprising:
one or more transistors with a gate having a gate stack including
a fin including a group III—V based semiconductor substrate,
a high-kappa dielectric material layer in contact with and conformally covering the fin, and
a ruthenium-phosphorus (Ru—P) thin film in contact with and conformally covering the high-kappa dielectric material layer; and
a single layer of gate material adjacent to and in contact with the Ru—P thin film, wherein the Ru—P thin film is to function as a diffusion barrier, a nucleation layer, a conductive liner, and an adhesion layer; and
electrical circuitry coupled to the one or more transistors.
11. The semiconductor device of claim 10 , wherein the one or more transistors are one or more tri-gate transistors, and the semiconductor substrate is a fin of the tri-gate transistor.
12. The semiconductor device of claim 10 , wherein the Ru—P thin film is approximately 1 to 5 nanometers thick, wherein the Ru—P thin film is deposited by a chemical vapor deposition (CVD) process, wherein the CVD process includes: placing the semiconductor device in a vacuum chamber, heating the semiconductor device at a temperature of approximately 200 to 450 degrees Celsius, depositing a ruthenium precursor on the high-kappa dielectric material layer, and curing the ruthenium precursor to form the Ru—P thin film.
13. The semiconductor device of claim 12 , wherein the precursor includes Ru(PF 3 ) 4 H 2 , cis-H 2 Ru(P(CH 3 ) 3 ) 4 , R 2 PCH 2 CH 2 PR 2 , R 2 PCH 2 CH 2 NHCH 2 CH 2 PR 2 , a bidentate ligand containing phosphorus, a tridentate ligand containing phosphorus, bis(cyclopentadienyl) ruthenium, a ruthenium amidinate complex, a ruthenium diazadiene complex, a ruthenium carbonyl complex, or bis(R-cyclopentadienyl) ruthenium, and wherein R is methyl, ethyl, propyl, isopropyl or t-butyl.
14. The semiconductor device of claim 12 , wherein the depositing of the ruthenium precursor includes co-flow of a co-reactant, wherein the co-reactant includes hydrogen (H 2 ), ammonia (NH 3 ), phosphine (PH 3 ), monoalkylphosphine (H 2 PR), dialkylphosphine (HPRR′), or trialkylphosphine (PRR′R″), or a substituted or unsubstituted hydrazine, wherein R, R′ and R″ are methyl, ethyl, propyl, isopropyl, or t-butyl.
15. The semiconductor device of claim 12 , wherein the depositing of the ruthenium precursor includes plasma enhanced CVD and co-flow of co-reactant ammonia.
16. The semiconductor device of claim 10 , further comprising:
a liner disposed between and coupled to the high-kappa dielectric material layer and the Ru—P thin film.
17. A semiconductor device, comprising:
a nanowire substrate;
a high-kappa dielectric material layer surrounding the nanowire substrate, and adjacent to and in contact with the nanowire substrate;
a ruthenium-phosphorus (Ru—P) thin film surrounding the high-kappa dielectric material layer, and adjacent to and in contact with the high-kappa dielectric material layer; and
a single metal layer adjacent to and in contact with the Ru—P thin film, wherein the Ru—P thin film is to function as a diffusion barrier, a nucleation layer, a conductive liner, and an adhesion layer.
18. The semiconductor device of claim 17 , wherein the nanowire substrate is composed of silicon, silicon germanium, germanium, or a Group III-V semiconductor.
19. The semiconductor device of claim 17 , wherein the Ru—P thin film is approximately 1 to 5 nanometers thick, wherein the Ru—P thin film is deposited by a chemical vapor deposition (CVD) process, wherein the CVD process includes: placing the semiconductor device in a vacuum chamber, heating the semiconductor device at a temperature of approximately 200 to 450 degrees Celsius, depositing a ruthenium precursor on the high-kappa dielectric material layer, and curing the ruthenium precursor to form the Ru—P thin film.