Magnetic memory devices with enhanced tunnel magnetoresistance ratio (TMR) and methods of fabrication

1. A memory device, comprising:

a first electrode;

a conductive layer comprising iridium and iron above the first electrode, wherein the conductive layer is a single conductive layer, wherein the conductive layer comprises up to 1 atomic percent of iron and wherein the atomic percent of iron varies from an uppermost surface to a lowermost surface of the conductive layer;

a magnetic junction on the conductive layer, the magnetic junction comprising:

a magnetic structure, comprising:

a first magnetic layer comprising cobalt;

a non-magnetic layer on the first magnetic layer; and

a second magnetic layer comprising cobalt, the second magnetic layer on the non-magnetic layer, wherein the magnetic structure has antiferromagnetic properties;

an anti-ferromagnetic layer on the magnet structure;

a first magnet with a first magnetization, the first magnet above the anti-ferromagnetic layer, wherein the first magnetization is a fixed magnetization;

a second magnet with a second magnetization, the second magnet above the first magnet, wherein the second magnetization is a free magnetization;

a layer between the first magnet and the second magnet; and

a second electrode above the magnetic junction.

2. The memory device of claim 1 , wherein the non-magnetic layer comprises platinum or tungsten.

3. The memory device of claim 2 , wherein the non-magnetic layer comprising platinum has a thickness of at least 0.015 nm but less than 0.4 nm.

4. The memory device of claim 2 , wherein the non-magnetic layer comprising tungsten has a thickness of at least 0.01 nm but less than 0.4 nm.

5. The memory device of claim 1 , wherein the first magnetic layer has a thickness between 0.4 nm and 2 nm.

6. The memory device of claim 1 , wherein the second magnetic layer has a thickness between 0.4 nm and 2 nm.

7. The memory device of claim 1 , wherein the non-magnetic layer is a first non-magnetic layer and the memory device further comprises:

a second non-magnetic layer on the second magnetic layer; and

a third magnetic layer on the second non-magnetic layer.

8. The memory device of claim 7 , wherein the second non-magnetic layer comprises tungsten, wherein the tungsten has a thickness between 0.1 nm and 0.4 nm.

9. The memory device of claim 1 , wherein the anti-ferromagnetic layer comprises ruthenium or iridium.

10. The memory device of claim 9 , wherein the iridium has a thickness of approximately 0.5 nm or approximately 1.4 nm, and wherein the ruthenium has a thickness of approximately 0.4 nm or approximately 0.8 nm.

11. The memory device of claim 1 , wherein the conductive layer comprises cobalt, wherein the atomic percent of cobalt varies from an uppermost surface to a lowermost surface of the conductive layer, and wherein a concentration of cobalt varies by up to 1% where a high concentration is at an uppermost surface and a low concentration is at a lowermost surface.

12. The memory device of claim 1 , wherein the conductive layer has a thickness between 0.5 nm and 5 nm and a face centered cubic <111>crystal texture.

13. A memory device, comprising:

a first electrode;

a conductive layer comprising iridium and iron above the first electrode, wherein the conductive layer is a single conductive layer, wherein the conductive layer comprises up to 1 atomic percent of iron and wherein the atomic percent of iron varies from an uppermost surface to a lowermost surface of the conductive layer;

a magnetic junction on the conductive layer, the magnetic junction comprising:

a magnetic structure comprising:

a first magnetic layer comprising cobalt;

a first non-magnetic layer comprising platinum on the first magnetic layer;

a second magnetic layer comprising cobalt, the second magnetic layer on the first non-magnetic layer;

a second non-magnetic layer comprising tungsten, the second non-magnetic layer on the second magnetic layer; and

a third magnetic layer on the second non-magnetic layer;

a spacer layer on the first magnet structure;

a conductive structure on the spacer layer;

a first magnet with a first magnetization above the conductive structure,

wherein the first magnetization is a fixed magnetization;

a second magnet with a second magnetization, the second magnet above the first

magnet, wherein the second magnetization is a free magnetization;

a layer between the first magnet and the second magnet; and

a second electrode above the magnetic junction.

14. The memory device of claim 13 , wherein the conductive layer has a thickness between 0.5 nm and 5 nm.

15. The memory device of claim 13 , wherein the first magnetic layer has a thickness between 0.4 to 1.5 nm and the second magnetic layer has a thickness between 0.4 nm and 1.5 nm.

16. The memory device of claim 13 , wherein the first non-magnetic layer has a thickness of at least 0.015 nm but less than 0.4 nm and the second non-magnetic layer has a thickness between 0.1 nm and 0.4 nm.

17. The memory device of claim 13 , wherein the conductive structure comprises:

a fourth magnetic layer comprising cobalt, wherein the magnetic layer has a thickness between 0.5 nm and 1 nm; and

a third nonmagnetic layer includes tantalum, molybdenum or tungsten, wherein the third nonmagnetic layer has a thickness of at least 0.1 nm.

18. The memory device of claim 13 , wherein the spacer layer comprises iridium, wherein the iridium has a thickness of approximately 0.5 nm or approximately 1.4 nm, or spacer layer comprises ruthenium, wherein the ruthenium has a thickness of approximately 0.4 nm or approximately 0.8 nm.

19. A system, comprising:

a transistor above a substrate, the transistor comprising:

a drain contact coupled to a drain;

a source contact coupled to a source;

a gate contact coupled to a gate; and

a bottom electrode coupled to the drain contact;

a memory device, coupled with the drain contact, the memory device comprising:

a first electrode;

a buffer layer on the first electrode;

a conductive layer comprising iridium and iron above the first electrode, wherein the conductive layer is a single conductive layer, wherein the conductive layer comprises up to 1 atomic percent of iron and wherein the atomic percent of iron varies from an uppermost surface to a lowermost surface of the conductive layer;

a magnetic tunnel junction (MTJ) on the conductive layer, the MTJ comprising:

a magnetic structure comprising:

a first magnetic layer comprising cobalt;

a non-magnetic layer on the first magnetic layer; and

a second magnetic layer comprising cobalt, the second magnetic layer on the non-magnetic layer, wherein the magnetic structure has antiferromagnetic properties;

an anti-ferromagnetic layer on the magnetic layer;

a first magnet with a first magnetization, the first magnet is above the anti-ferromagnetic layer, wherein the first magnetization is a fixed magnetization;

a second magnet with a second magnetization, the second magnet above the first magnet, wherein the second magnetization is a free magnetization;

a tunnel barrier between the first magnet and the second magnet; and

a second electrode on the MTJ.

20. The system of claim 19 , further comprising a power supply coupled to the transistor, wherein the first and second magnetizations are perpendicular to a plane of the memory device.