Circuits and methods for reducing minimum supply for register file cells
A register file employing a shared supply structure to improve the minimum supply voltage.
1. An apparatus comprising:
a memory cell;
a switch, coupled to the memory cell, to provide a cell supply to the memory cell; and
a logic, coupled to the switch to control the switch, to reduce the cell supply for a duration according to an operational frequency.
2. The apparatus of claim 1 , wherein the memory cell is a 6T SRAM cell.
3. The apparatus of claim 1 , wherein the switch is coupled to:
a first node to provide the cell supply, and
a second node to receive a power supply.
4. The apparatus of claim 3 , wherein the logic is to cause the switch to decouple the first node from the second node.
5. The apparatus of claim 1 , wherein the duration is programmable.
6. The apparatus of claim 1 , wherein the memory cell is positioned in a column of memory cells.
7. The apparatus of claim 1 , wherein the logic is operable to adjust pulse width of a control signal provided to the switch to reduce the cell supply.
8. The apparatus of claim 1 , wherein the memory cell, the switch, and the logic are positioned in a processor.
9. The apparatus of claim 8 , wherein the processor is one of:
a programmable logic array;
a memory;
a network chip; or
a controller.
10. The apparatus of claim 8 , wherein the processor is positioned in one of:
a laptop computer;
a phone; or
audio and/or video player.
11. The apparatus of claim 8 further comprises an antenna to wirelessly couple the processor to a wireless network.
12. The apparatus of claim 11 , wherein the wireless network is a wireless local area network or a cellular network.
13. The apparatus of claim 1 , wherein the memory cell is one of:
a dynamic random access memory cell;
a static random access memory cell; or
a flash memory cell.
14. An apparatus comprising:
a first power supply node to provide a first power supply;
a second power supply node;
a memory cell coupled to the second power supply node; and
a switch, coupled to the first and second power supply nodes, the switch to control voltage level of a second power supply of the second power supply node for a duration according to an operational frequency.
15. The apparatus of claim 14 , wherein the memory cell is positioned in a column of memory cells.
16. The apparatus of claim 14 , wherein the switch comprises one or more p-type transistors.
17. The apparatus of claim 14 further comprises logic to provide a control signal, of a controllable pulse width, for controlling the switch.
18. An apparatus comprising:
a memory cell;
a switch, coupled to the memory cell, the switch to control voltage level of a first power supply provided to the memory cell; and
a logic to adjust a pulse width, of a control signal provided to the switch, for a duration according to an operational frequency for writing data into the memory cell.
19. The apparatus of claim 18 , wherein the memory cell is a 6T SRAM cell.
20. The apparatus of claim 18 , wherein the memory cell is positioned in a column of memory cells.