IP Library Granted Patent US 9,922,720
Granted Patent B2
US 9,922,720 · App. 13/788,028 · Granted Mar 20, 2018

Random fuse sensing

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Quick Facts
Patent No.
US 9,922,720
App. No.
13/788,028
Granted
Mar 20, 2018
Kind
B2
Abstract

In accordance with some embodiments, the way in which the fuses are sensed and, particularly, their order may be made more random so that it is much more difficult to simply exercise the device and determine all the values of the storage elements within the fuse array. One result is a more secure storage device.

Claims (32)

1. A computer executed method comprising:

randomly selecting a fuse address to begin fuse sensing; and

using a first string of bits to record a state, including at least one complement bit, and including storing said first string along an address line in a first direction and a second string that is a complement of the first string in an address line in a different direction.

2. The method of claim 1 including randomly selecting an initial row to sense.

3. The method of claim 2 including using a random number generator to select the row.

4. The method of claim 3 including using the generator to produce a seed for a counter.

5. The method of claim 3 including randomly repeatedly picking a different row to sense until all rows have been sensed.

6. The method of claim 5 including using a counter with a linear feedback shift register.

7. The method of claim 5 including randomly selecting one or more of a module, group, or block of rows to sense.

8. The method of claim 7 including randomly selecting each of a module, group, block, and row to sense.

9. The method of claim 1 including selecting fuse addresses in a first fuse array that has an on-die programmable fuse array and including a second fuse array that is only accessible separately from said first fuse array.

10. An apparatus comprising:

a random number generator;

a control to store a value along a first address line as a string of bits of at least two different states and to store a complement string along a second address line perpendicular to said first address line; and

a linear feedback shift register coupled to said generator.

11. The apparatus of claim 10 including a fuse array coupled to said register.

12. The apparatus of claim 11 wherein said register to randomly pick fuse array addresses.

13. The apparatus of claim 11 wherein said fuse array is an on-die programmable fuse array.

14. The apparatus of claim 13 including a second array that is not on-die programmable, said first and second arrays being password accessed using different passwords.

15. The apparatus of claim 10 including an operating system.

16. The apparatus of claim 10 including firmware and a module to update said firmware.

17. One or more non-transitory computer readable media storing instructions to enable a processor to perform a sequence comprising:

randomly selecting a fuse address to begin fuse sensing; and

providing a first string of bits to record a state, including at least one complement bit, and including storing said first string along an address line in a first direction and a second string that is a complement of the first string along an address line in a different direction.

18. The media of claim 17 , said sequence including randomly selecting an initial row to sense.

19. The media of claim 18 , said sequence including a random number generator to select the row.

20. The media of claim 19 , said sequence including using the generator to produce a seed for a counter.

21. The media of claim 19 , said sequence including randomly repeatedly picking a different row to sense until all rows have been sensed.

22. The media of claim 21 , said sequence including using a counter with a linear feedback shift register.

23. The media of claim 21 , said sequence including randomly selecting one or more of a module, group, or block of rows to sense.

24. The media of claim 23 , said sequence including randomly selecting each of a module, group, block, and row to sense.

25. The media of claim 17 , said sequence including selecting fuse addresses in a first fuse array that has an on-die programmable fuse array and including a second fuse array that is only accessible separately from said first fuse array.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 15, 2022
From: INTEL CORPORATION
To: TAHOE RESEARCH, LTD.
Reel/Frame 061175/0176 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 10, 2013
From: SANDRI, JASON G.; ABU, HORAIRA; PETERSON, CHARLES A.; PEDERSEN, MATTHEW B.; HARRIS, BRIAN; WALKER, IAN S.; AHMED, MONIB
To: INTEL CORPORATION
Reel/Frame 030577/0012 →