Localized spacer for a multi-gate transistor

1. A method comprising:

forming a buried oxide layer on a substrate;

forming a silicon layer on the buried oxide layer;

forming first and second insulation layers on the silicon layer;

patterning the first and second insulation layers and the silicon layer to form a stack;

depositing and polishing a polysilicon layer on both sides of the stack to a level of the second insulation layer of the stack;

depositing a hard mask layer;

selectively removing a portion of the hard mask layer and the second insulation layer to form a pair of self-aligned spacer structures over respective portions of the silicon layer; and

patterning the polysilicon layer to form a pair of gates and expose a portion of the silicon layer not covered by the self-aligned spacer structures.

2. The method of claim 1 , further comprising performing a tip implantation to implant tip material into the exposed portion of the silicon layer.

3. The method of claim 2 , wherein the self-aligned spacer structures are to block the tip material from impinging into at least a portion of the silicon layer under the second insulation layer.

4. The method of claim 1 , further comprising forming the self-aligned spacer structures with a tapered profile.

5. The method of claim 4 , further comprising adjusting an etch density of an etch process to provide the tapered profile.

6. The method of claim 5 , further comprising adjusting a radio frequency of the etch process to provide the tapered profile.

7. The method of claim 3 , further comprising forming a double gate transistor with the pair of gates.