Dielectric and isolation lower Fin material for Fin-based electronics
A dielectric and isolation lower fin material is described that is useful for fin-based electronics. In some examples, a dielectric layer is on first and second sidewalls of a lower fin. The dielectric layer has a first upper end portion laterally adjacent to the first sidewall of the lower fin and a second upper end portion laterally adjacent to the second sidewall of the lower fin. An isolation material is laterally adjacent to the dielectric layer directly on the first and second sidewalls of the lower fin and a gate electrode is over a top of and laterally adjacent to sidewalls of an upper fin. The gate electrode is over the first and second upper end portions of the dielectric layer and the isolation material.
1. A method comprising:
forming a fin on a substrate;
depositing a glass of a first dopant type over the substrate and over a lower portion of the fin;
depositing a glass of a second dopant type over the substrate and the fin;
annealing the glass to drive the dopants into the fin and the substrate;
removing the glass; and
forming a first and a second contact over the fin without contacting the lower portion of the fin.
2. The method of claim 1 , further comprising forming a control gate over the fin, the control gate being a conductive material over the top and on the sides of the fin to control current flow through the fin between the first and second contacts.
3. The method of claim 1 , wherein forming a control gate comprises patterning polysilicon over the fin, removing the polysilicon and backfilling the void from the polysilicon with metal.
4. The method of claim 1 , wherein forming a control gate comprises forming a control gate over the fin after removing the glass and before forming the first and second contacts.
5. The method of claim 1 , wherein the first contact comprises a source, the second contact comprises a drain, the method further comprising forming a gate over the fin between the source and the drain without contacting the lower portion of the fin.
6. The method of claim 5 , further comprising depositing an oxide over the silicon substrate after removing the glass, the oxide having a depth to cover the lower portion of the fin, the oxide isolating the lower portion of the fin before forming the doped source, gate, and drain.
7. The method of claim 1 , wherein depositing a glass of a first dopant type comprises:
depositing the glass of the first dopant type over the substrate and the fin;
depositing a blocking material over the substrate and a portion of the fin;
removing the deposited glass that is not covered in the blocking material; and
removing the blocking material.
8. The method of claim 7 , wherein depositing glass of a second dopant type comprises removing the glass of the first dopant type from a portion of the fin and depositing the glass of the second dopant type over the portion of the fin and over the glass of the first dopant type.
9. A method of fabricating an integrated circuit structure, the method comprising:
forming a fin comprising silicon, the fin having a lower fin portion and an upper fin portion;
forming a layer comprising a phosphosilicate glass (PSG), the layer comprising the PSG directly on first and second sidewalls of the lower fin portion of the fin, the layer comprising the PSG having a first upper end portion laterally adjacent to the first sidewall of the lower fin portion of the fin, and the layer comprising the PSG having a second upper end portion laterally adjacent to the second sidewall of the lower fin portion of the fin;
forming an isolation material comprising oxygen, the isolation material laterally adjacent to the layer comprising the PSG directly on the first and second sidewalls of the lower fin portion of the fin, the isolation material having a first upper surface portion and a second upper surface portion, wherein the first upper surface portion of the isolation material is below the first upper end portion of the layer comprising the PSG, and wherein the second upper surface portion of the isolation material is below the second upper end portion of the layer comprising the PSG; and
forming a gate electrode over a top of and laterally adjacent to sidewalls of the upper fin portion of the fin, and the gate electrode over the first and second upper end portions of the layer comprising the PSG, and the gate electrode over the first and second upper surface portions of the isolation material.
10. The method of claim 9 , wherein the first upper surface portion of the isolation material is laterally adjacent to the layer comprising the PSG on the first sidewall of the lower fin portion of the fin.
11. The method of claim 10 , wherein the second upper surface portion of the isolation material is laterally adjacent to the layer comprising the PSG on the second sidewall of the lower fin portion of the fin.
12. The method of claim 9 , further comprising:
forming an insulating layer directly laterally adjacent to the layer comprising the PSG directly on the first and second sidewalls of the lower fin portion of the fin, wherein the isolation material is directly laterally adjacent to the insulating layer.
13. The method of claim 12 , wherein the insulating layer comprises a borosilicate glass (BSG).
14. The method of claim 12 , wherein the insulating layer has a first upper end portion laterally adjacent to the first upper end portion of the layer comprising the PSG, and wherein the insulating layer has a second upper end portion laterally adjacent to the second upper end portion of the layer comprising the PSG.
15. A method of fabricating an integrated circuit structure, the method comprising:
forming a fin comprising silicon, the fin having a lower fin portion and an upper fin portion;
forming a dielectric layer comprising a P-type dopant, the dielectric layer directly on first and second sidewalls of the lower fin portion of the fin, the dielectric layer having a first upper end portion laterally adjacent to the first sidewall of the lower fin portion of the fin, and the dielectric layer having a second upper end portion laterally adjacent to the second sidewall of the lower fin portion of the fin;
forming an isolation material comprising oxygen, the isolation material laterally adjacent to the dielectric layer directly on the first and second sidewalls of the lower fin portion of the fin, the isolation material having a first upper surface portion and a second upper surface portion, wherein the first upper surface portion of the isolation material is below the first upper end portion of the dielectric layer, and wherein the second upper surface portion of the isolation material is below the second upper end portion of the dielectric layer; and
forming a gate electrode over a top of and laterally adjacent to sidewalls of the upper fin portion of the fin, and the gate electrode over the first and second upper end portions of the dielectric layer, and the gate electrode over the first and second upper surface portions of the isolation material.
16. The method of claim 15 , wherein the P-type dopant is boron.
17. The method of claim 15 , wherein the first upper surface portion of the isolation material is laterally adjacent to the dielectric layer on the first sidewall of the lower fin portion of the fin.
18. The method of claim 17 , wherein the second upper surface portion of the isolation material is laterally adjacent to the dielectric layer on the second sidewall of the lower fin portion of the fin.
19. The method of claim 15 , further comprising:
forming an insulating layer directly laterally adjacent to the dielectric layer directly on the first and second sidewalls of the lower fin portion of the fin, wherein the isolation material is directly laterally adjacent to the insulating layer.
20. The method of claim 19 , wherein the insulating layer has a first upper end portion laterally adjacent to the first upper end portion of the dielectric layer, and wherein the insulating layer has a second upper end portion laterally adjacent to the second upper end portion of the dielectric layer.