Flexible command addressing for memory
Flexible command addressing for memory. An embodiment of a memory device includes a dynamic random-access memory (DRAM); and a system element coupled with the DRAM, the system element including a memory controller for control of the DRAM. The DRAM includes a memory bank, a bus, the bus including a plurality of pins for the receipt of commands, and a logic, wherein the logic provides for shared operation of the bus for a first type of command and a second type of command received on a first set of pins.
1. A dynamic random access memory (DRAM) chip comprising:
a memory bank to store data; and
hardware logic to receive commands via command/address (CA) pins to access the memory bank, the hardware logic to:
receive a first command, including receipt of a row address via a plurality of the CA pins, and determine the first command comprises an ACTIVATE command based at least in part on detection of a logic LOW on a first CA pin and a logic HIGH on a second CA pin;
receive a second command, including receipt of a column address via one or more of the plurality of CA pins, and determine the second command comprises a READ or WRITE command based at least in part on detection of a logic HIGH on the first CA pin and a logic LOW on the second CA pin; and
receive a third command, and determine the third command comprises a No-operation (NOP) command based at least in part on detection of a logic HIGH on the first CA pin and a logic HIGH on the second CA pin;
wherein the hardware logic is to receive the following over a same CA pin: a column address bit for the READ or WRITE command, a row address bit for the ACTIVATE command, and a command encoding bit for the ACTIVATE, READ or WRITE, and NOP commands.
2. The DRAM chip of claim 1 , wherein:
the first CA pin comprises a lowest of a sequential ordering of CA pins and the second CA pin comprises a second lowest of the sequential ordering of CA pins.
3. The DRAM chip of claim 2 , wherein:
the first CA pin comprises CA[0] and the second CA pin comprises CA[1].
4. The DRAM chip of claim 1 , wherein:
the CA pin is CA[1].
5. The DRAM chip of claim 1 , wherein:
the CA pins comprise a CA bus for one of multiple channels.
6. The DRAM chip of claim 1 , wherein:
the DRAM chip comprises a Wide Input/Output (IO) compatible device.
7. A system comprising:
a stack of DRAM memory chips;
a memory controller coupled with the stack of DRAM memory chips to control the DRAM memory chips, wherein a DRAM memory chip comprises:
a memory bank to store data; and
hardware logic to receive commands via command/address (CA) pins to access the memory bank, the hardware logic to:
receive a first command, including receipt of a row address via a plurality of the CA pins, and determine the first command comprises an ACTIVATE command based at least in part on detection of a logic LOW on a first CA pin and a logic HIGH on a second CA pin;
receive a second command, including receipt of a column address via one or more of the plurality of CA pins, and determine the second command comprises a READ or WRITE command based at least in part on detection of a logic HIGH on the first CA pin and a logic LOW on the second CA pin; and
receive a third command, and determine the third command comprises a No-operation (NOP) command based at least in part on detection of a logic HIGH on the first CA pin and a logic HIGH on the second CA pin;
wherein the hardware logic is to receive the following over a same CA pin: a column address bit for the READ or WRITE command, a row address bit for the ACTIVATE command, and a command encoding bit for the ACTIVATE, READ or WRITE, and NOP commands.
8. The system of claim 7 , wherein:
the first CA pin comprises a lowest of a sequential ordering of CA pins and the second CA pin comprises a second lowest of the sequential ordering of CA pins.
9. The system of claim 8 , wherein:
the first CA pin comprises CA[0] and the second CA pin comprises CA[1].
10. The system of claim 7 , wherein:
the CA pin is CA[1].
11. The system of claim 7 , wherein:
the CA pins comprise a CA bus for one of multiple channels.
12. The system of claim 7 , wherein:
a DRAM chip comprises a Wide Input/Output ( 10 ) compatible device.
13. The system of claim 7 , further comprising:
a processor.
14. The system of claim 13 , wherein:
the processor comprises the memory controller.
15. The system of claim 13 , wherein:
the processor comprises one or more of a central processing unit (CPU) or a graphics processing unit (GPU).
16. The system of claim 13 , further comprising:
a system on a chip (SoC), the SoC including the processor.
17. The system of claim 13 , wherein:
the processor and the stack of DRAM chips are in a same package.
18. The system of claim 7 , further comprising:
a through silicon via (TSV) through the stack of DRAM chips to couple the DRAM chips with the memory controller.
19. The system of claim 7 , further comprising one or more of: a display, an antenna, a battery.
20. A method comprising:
receiving a first command via command/address (CA) pins of a DRAM chip, including receiving a row address via a plurality of the CA pins;
determining the first command comprises an ACTIVATE command based at least in part on detecting a logic LOW on a first CA pin and a logic HIGH on a second CA pin;
receiving a second command, including receiving a column address via one or more of the plurality of CA pins;
determining the second command comprises a READ or WRITE command based at least in part on detecting a logic HIGH on the first CA pin and a logic LOW on the second CA pin;
receiving a third command; and
determining the third command comprises a No-operation (NOP) command based at least in part on detecting a logic HIGH on the first CA pin and a logic HIGH on the second CA pin;
wherein receiving the first, second, and third commands includes receiving the following over a same CA pin: a column address bit for the READ or WRITE command, a row address bit for the ACTIVATE command, and a command encoding bit for the ACTIVATE, READ or WRITE, and NOP commands.