Address decoding method, and memory controller and semiconductor memory system using the same
A semiconductor memory system includes a memory device including plural banks, and a memory controller that generates an offset address for a first bank among the plural banks and a command indicating the offset address, based on a first request. The memory device generates a first address by adding the offset address to a base address for the first bank, according to the command, and performs a memory operation on the first address of the first bank according to the command.
1 . A semiconductor memory system comprising:
a memory device comprising a plurality of banks; and
a memory controller configured to generate an offset address for a first bank among the plurality of banks and a command indicating the offset address, based on a first request, and transmit the offset address and the command to the memory device,
wherein the memory device is configured to receive the offset address and the command, generate a first address by adding the offset address to a base address for the first bank, according to the command, and perform a memory operation on the first address of the first bank according to the command.
2 . A semiconductor memory system comprising:
a memory device comprising a plurality of banks; and
a memory controller configured to generate an offset address for a first bank among the plurality of banks and a command indicating the offset address, based on a first request,
wherein:
the memory device is configured to generate a first address by adding the offset address to a base address for the first bank, according to the command, and perform a memory operation on the first address of the first bank according to the command,
when an address in the first bank that corresponds to the first request is within an offset range with respect to a second address in the first bank that corresponds to a second request immediately before the first request, the memory controller generates the offset address for the first bank with respect to the second address, and
the base address is the second address.
3 . The semiconductor memory system of claim 2 , wherein:
the command comprises at least one of:
an Offset-Activate command indicating an activate operation using the offset address, the Offset-Activate command comprising a command delimiter, a bank address, and an offset;
an Offset-Read command indicating a read operation using the offset address, the Offset-Read command comprising a command delimiter, a bank address, and an offset; and
an Offset-Write command indicating a write operation using the offset address, the Offset-Write command comprising a command delimiter, a bank address, and an offset.
4 . The semiconductor memory system of claim 3 , wherein:
the command comprises the Offset-Activate command, the Offset-Read command, and the Offset-Write command,
the offset of the Offset-Activate command is an offset row address, and
the offset of each of the Offset-Read command and the Offset-Write command is an offset column address.
5 . The semiconductor memory system of claim 2 , wherein:
the command comprises at least one of:
an Offset-Activate command indicating an activate operation using the offset address, the Offset-Activate command comprising a command delimiter and a bank address;
an Offset-Read command indicating a read operation using the offset address, the Offset-Read command comprising a command delimiter and a bank address;
an Offset-Write command indicating a write operation using the offset address, the Offset-Write command comprising a command delimiter and a bank address; and
a Set-Offset command comprising a command delimiter, a bank address, and an offset.
6 . The semiconductor memory system of claim 5 , wherein:
the command comprises the Set-Offset command, and
the offset of the Set-Offset command has a fixed value corresponding to the offset address.
7 . The semiconductor memory system of claim 2 , wherein:
the memory device comprises an address decoder configured to identify the offset address for the first bank by decoding the command, and generate the first address by adding the offset address to the second address.
8 . The semiconductor memory system of claim 7 , wherein the address decoder comprises:
an address table that stores, for each of the plurality of banks, a base row address for a memory row that was driven last for the first bank and a base column address for a memory column that was driven last for the bank;
a row/column selector configured to provide one of a base row address and a base column address in the address table that corresponds to the first bank; and
an address summer configured to generate the first address by adding the offset address to the one of the base row address and the base column address provided from the row/column selector.
9 . The semiconductor memory system of claim 8 , wherein
when the command indicates an offset row address, the row/column selector provides the base row address to the address summer, and the address summer generates the first address by adding the offset address to the base row address.
10 . The semiconductor memory system of claim 8 , wherein:
when the command indicates an offset column address, the row/column selector provides the base column address to the address summer, and the address summer generates the first address by adding the offset address to the base column address.
11 . The semiconductor memory system of claim 8 , wherein:
the address decoder further comprises an address demultiplexer configured to update the first address in the address table with the one of a base row address and a base column address corresponding to the first bank.
12 . The semiconductor memory system of claim 8 , wherein:
the address decoder further comprises an address multiplexer configured to output the first address provided from the address summer when the first address is within the offset range, and output the first address provided from the memory controller when the first address is not within the offset range.
13 . The semiconductor memory system of claim 1 , wherein:
the command indicates the memory operation and the memory operation corresponds to the offset address, and
the command comprises a plurality of signals comprising a chip select signal provided to the memory device in a double data rate mode.
14 . An address decoding method comprising:
receiving, from a memory controller, a command and an address;
decoding the command;
when the command indicates the address comprises an offset row address, generating a row address by adding the offset row address to a base row address for a memory row that was driven last in a bank corresponding to the address; and
when the command indicates the address comprises an offset column address, generating a column address by adding the offset column address to a base column address for a memory column that was driven last in a bank corresponding to the address.
15 . The address decoding method of claim 14 , wherein an address table stores, for each bank of a plurality of banks, a base row address for a memory row of the bank that was driven last and a base column address for a memory column that was driven last, and
the address decoding method further comprises updating the address table with the row address or the column address of the bank that was generated.
16 . The semiconductor memory system of claim 1 , wherein the offset address comprises an address having a smaller number of bits than a full address.
17 . The address decoding method of claim 14 , wherein the offset address comprises an address having a smaller number of bits than a full address.