Operating system-independent method and system of determining CPU utilization
View Patent ↗A method and device are provided to monitor clock control signals from a CPU core; and calculate a time period during a sampling interval that the CPU core was used to perform work based on the clock control signals.
1. A method comprising:
monitoring clock control signals from a CPU core; and
calculating a time period during a sampling interval that the CPU core has requested a clock control unit to allow clock signals to be asserted.
2. The method of claim 1 , wherein the monitoring comprises receiving, in a clock control unit, halt and break signals from the CPU core that cause the clock control unit to respectively start and stop a clock signal to the CPU core; and generating a clock control unit signal based on the halt and break signals, the clock control unit signal indicating a number of times during the sampling interval that the clock signal to the CPU core was started.
3. The method of claim 2 , wherein the monitoring further comprises sending the clock control unit signal to a performance monitoring unit in the bus interface, which performance monitoring unit is part of performance monitoring logic to monitor configurable events relating to CPU performance.
4. The method of claim 3 , wherein the monitoring further comprises configuring the performance monitoring unit to drive the clock control unit signal onto a performance monitoring bus which facilitates communications between components of the performance monitoring logic.
5. The method of claim 4 , wherein the monitoring further comprises configuring a register of the performance monitoring logic to increment when the performance monitoring bus unit drives the clock control unit signal onto the performance monitoring bus.
6. The method of claim 5 , wherein the calculating comprises reading the register once in the sampling interval; and dividing the reading by the sampling interval to get an effective frequency for the CPU core.
7. The method of claim 6 , further comprising resetting the register after each reading thereof.
8. The method of claim 2 , wherein the clock control unit is integrated in a bus interface which bridges communications between a processor system bus and the CPU core.
9. A method comprising:
configuring a performance monitor to monitor an event indicating when a clock signal to a CPU core is stopped;
reading the performance monitor once during a sampling time interval to obtain a value; and
calculating an effective frequency of the CPU core by dividing the value by the sampling time interval.
10. The method of claim 9 , wherein the event is an event known as CPU_CLKS_UNHALTED.
11. The method of claim 10 further comprising:
resetting the performance monitor after the reading; and
repeating the reading of the performance monitor once during the sampling time interval to obtain the value, and the calculating of the effective frequency of the CPU core by dividing the value by the sampling time interval, for each sampling time interval.
12. The method of claim 11 , further comprising expressing the effective frequency as a percentage of an actual frequency for the CPU core.
13. A method comprising:
determining a type of a microprocessor operating in a system;
if the type is of a predefined type, then configuring a performance monitor to monitor an event indicating when a clock signal to a CPU is stopped;
reading the performance monitor once during a sampling time interval to obtain a value; and
calculating an effective frequency for the CPU core by dividing the value by the sampling time interval.
14. The method of claim 13 , wherein the event is the event known as CPU_CLKS_UNHALTED.
15. The method of claim 14 , wherein the reading of the performance monitor once during the sampling time interval to obtain the value, and the calculating of the effective frequency for the CPU core by dividing the value by the sampling time interval, are performed only if the CPU core is not in a low power state.
16. A tangible computer-readable medium having stored thereon a sequence of instructions which when executed by a processing system cause the system to perform a method comprising:
monitoring clock control signals from a CPU core; and
calculating a time period during a sampling interval that the CPU core has requested a clock control unit to allow clock signals to be asserted.
17. The computer-readable medium of claim 16 , wherein the monitoring comprises receiving, in a clock control unit, halt and break signals from the CPU core that cause the clock control unit to respectively stop and start a clock signal to the CPU core; and generating a clock control signal based on the halt and break signals, the clock control unit signal indicating a number of times during the sampling interval that the clock signals to the CPU core was started.
18. The computer-readable medium of claim 17 , wherein the monitoring further comprises sending the clock control unit signal to a performance monitoring unit in the bus interface, which performance monitoring unit is part of performance monitoring logic to monitor configurable events relating to CPU performance.
19. The computer-readable medium of claim 18 , wherein the monitoring further comprises configuring the performance monitoring unit to drive the clock control unit signal onto a performance monitoring bus which facilitates communications between components of the performance monitoring logic.
20. The computer-readable medium of claim 17 , wherein the clock control unit is integrated in a bus interface which bridges communications between a processor system bus and the CPU core.
21. A tangible computer-readable medium having stored thereon a sequence of instructions which when executed by a processing system, cause the system to perform a method comprising:
configuring a performance monitor to monitor an event indicating when a clock signal to a CPU core is de-asserted;
reading the performance monitor once during a sampling time interval to obtain a value; and
calculating an effective frequency of the CPU core by dividing the value by the sampling time interval.
22. The computer-readable medium of claim 21 , wherein the event is an event known as CPU_CLKS_UNHALTED.
23. A computer-readable medium having stored thereon a sequence of instructions which when executed by a processing system cause a system to perform a method comprising:
determining a type of a microprocessor operating in a system;
if the type is of a predefined type, then configuring a performance monitor to monitor and event indicating that a clock signal to a CPU is stopped;
reading the performance monitor once during a sampling time interval to obtain a value; and
calculating an effective frequency for the CPU core by dividing the value by the time sampling interval.
24. The computer-readable medium of claim 23 , wherein the event is the event known as CPU_CLKS_UNHALTED.
25. The computer-readable medium of claim 23 , wherein the configuring of the performance monitor to monitor the event indicating when the clock signal to the CPU core is de-asserted, and the reading of the performance monitor once during the sampling time interval to obtain the value, are performed only if the CPU core is not in a low power state.