Self-aligned insulating etchstop layer on a metal contact

1. A method for forming a self-aligned insulating layer on a metal gate structure, the method comprising

providing a substrate having a transistor that includes a sacrificial gate structure;

forming a first oxide layer over the substrate;

removing the sacrificial gate structure into the first via;

depositing a metal gate structure into the first via;

selectively functionalizing the first oxide layer, but not the metal gate structure, with a silane selected from the group consisting of alkylsilane and perfluoroalkylsilane to inhibit nucleation of a non-conductive metal oxide layer; and

growing a non-conductive metal oxide layer on the metal gate structure and not the functionalized first oxide layer.

2. The method of claim 1 , further comprising removing the silane from the first oxide after growing the non-conductive metal oxide layer on the metal gate structure.

3. The method of claim 2 , further comprising:

forming a second oxide layer over the first oxide layer after removal of the silane;

etching the first and second oxide layers to form a second via contacting a source drain (S/D) region of the transistor; and

depositing a second metal in the second via to form S/D contacts to the S/D region, wherein the non-conductive metal oxide layer prevents a short between the metal gate structure and the S/D contacts.

4. The method of claim 1 , wherein the non-conductive metal oxide layer comprises at least one of HfO 2 , ZrO 2 , HfSiO, ZrSiO or a combination thereof.

5. The method of claim 1 , further comprising growing the non-conductive metal oxide layer on the metal gate structure by atomic layer deposition.

6. The method of claim 1 , wherein the possesses three hydrolytically sensitive Si—X linkages, wherein X comprises at least one of Cl, OMe, OEt, or NMe 2 , and wherein Me is a methyl group, and Et is an ethyl group.

7. The method of claim 1 , wherein the sacrificial gate structure comprises substantially vertical polysilicon sidewalls with non-conductive spacer layers formed adjacent to the substantially vertical sidewalls of the sacrificial gate structure.

8. The method of claim 7 , wherein the non-conductive spacer layers comprise SiN.

9. The method of claim 3 , wherein the first metal and the second metal are deposited in the first and second vias by electroless plating.