Tile-level snapback detection through coupling capacitor in a cross point array

1. An apparatus comprising:

a phase-change memory array having a tile that includes a plurality of memory cells; and

a decoder including:

a decoding path having a sense node configured to manifest a first voltage;

a capacitor coupled with the sense node at a first terminal and configured to provide a second voltage based on the first voltage; and

a logic circuit coupled with the capacitor at a second terminal and configured to control a latch based on a received enable signal and the second voltage.

2. The apparatus of claim 1 , wherein the apparatus comprises a phase-change memory and switch (PCMS) device.

3. The apparatus of claim 1 , wherein the capacitor is coupled to the sense node such that a change in the first voltage results in a corresponding change in the second voltage, wherein the first and second voltages have different values.

4. The apparatus of claim 1 , wherein the decoder further includes an initialization circuit coupled to the capacitor and configured to set the second voltage at an initial state prior to a detection of a snapback event.

5. The apparatus of claim 4 , wherein the initial state is ground.

6. The apparatus of claim 1 , wherein the logic circuit is configured to control the latch based on a result of an AND operation of the second voltage and the enable signal.

7. The apparatus of claim 1 , wherein the first voltage is a negative value before and after a snapback event.

8. The apparatus of claim 1 , wherein the capacitor has a capacitance of approximately 50 femtofarads.

9. A system comprising:

a phase-change memory (PCM) device including a decoder having:

a conditioning circuit configured to provide a non-negative sense voltage at a first node based on a negative sense voltage at a second node; and

a logic circuit configured to detect a snapback action based on the non-negative sense voltage and an enable signal; and

a storage controller coupled with the PCM device and configured to provide the enable signal wherein the conditioning circuit includes a capacitor coupled with the second node at a first terminal, and with the logic circuit at a second terminal.

10. The system of claim 9 , further comprising:

a decoding path having the second node to manifest the negative sense voltage.

11. The system of claim 10 , wherein the conditioning circuit includes a capacitor coupled to the first and second nodes and configured to provide the non-negative sense voltage to a first input of the logic circuit.

12. The system of claim 11 , wherein the conditioning circuit further comprises:

an initialization circuit configured to:

receive an initialization signal from the storage controller; and

set the non-negative voltage to an initial state based on the initialization signal.

13. The system of claim 9 , wherein the PCM device comprises a plurality of tiles and a plurality of decoders that respectively correspond to the plurality of tiles.

14. The system of claim 9 , wherein the system comprises a laptop computing device or a mobile computing device.

15. A method of detecting a snapback condition comprising:

selecting a memory cell of a tile by selectively driving a bitline and wordline with first and second voltages, respectively;

providing an enable signal to a logic circuit of a decoder of the tile;

providing a first positive sense voltage to the logic circuit based on a second negative sense voltage that is manifest at a sense node of a decoding path, wherein a change in the second sense voltage results in a corresponding change in the first sense voltage; and

latching a value output by the logic circuit.

16. The method of claim 15 , further comprising:

initializing the first voltage to a first state prior to said providing of the enable signal.

17. The method of claim 16 , wherein the first state is ground.

18. The method of claim 15 , wherein the second sense voltage is negative before and after a snapback event that occurs as a result of the selecting of the memory cell.

19. The method of claim 15 , further comprising:

providing the first sense voltage with a capacitor coupled with the sense node.

20. The method of claim 15 , further comprising:

disconnecting a decoder from the selected wordline prior to the selecting of the memory cell;

reconnecting the decoder to the selected wordline after a snapback event occurs, wherein the snapback event occurs as a result of the selecting of the memory cell; and

determining a set state of the memory cell based on the latched value.