Dopant diffusion barrier for source/drain to curb dopant atom diffusion
View Patent ↗An apparatus including a transistor device on a substrate including an intrinsic layer including a channel; a source and a drain on opposite sides of the channel; and a diffusion barrier between the intrinsic layer and each of the source and the drain, the diffusion barrier including a conduction band energy that is less than a conduction band energy of the channel and greater than a material of the source and drain. A method including defining an area of an intrinsic layer on a substrate for a channel of a transistor device; forming a diffusion barrier layer in an area defined for a source and a drain; and forming a source on the diffusion barrier layer in the area defined for the source and forming a drain in the area defined for the drain.
1. An apparatus comprising:
a substrate;
a transistor device on the substrate comprising:
an intrinsic layer comprising a channel;
a source material on a first side of the channel and a drain material on a second side of the channel; and
a diffusion barrier between the intrinsic layer and each of the source material and the drain material, the diffusion barrier comprising nitrogen and having a conduction band energy that is less than a conduction band energy of the channel and higher than a conduction band energy of the source material or the drain material.
2. The apparatus of claim 1 , wherein the intrinsic layer comprises a group III-V compound semiconductor material.
3. The apparatus of claim 2 , wherein the diffusion barrier comprises a dilute nitride alloy of the group III-V compound semiconductor of the intrinsic layer.
4. The apparatus of claim 1 , wherein the intrinsic layer comprises indium gallium arsenide (InGaAs) and the diffusion barrier comprises InGaAs 1-y N y , wherein y is less than 0.03.
5. The apparatus of claim 2 , wherein the source material and the drain material comprise a group III-V compound semiconductor material.
6. The apparatus of claim 5 , wherein the diffusion barrier comprises a group III-V compound semiconductor nitride alloy.
7. The apparatus of claim 1 , wherein the diffusion barrier comprises a pseudomorphic layer.
8. The apparatus of claim 1 , wherein the transistor comprises an N-type transistor.
9. An apparatus comprising:
a transistor comprising an intrinsic layer comprising an NMOS channel and a source and a drain formed in the intrinsic layer and a diffusion barrier layer between the intrinsic layer and each of the source and the drain, wherein the diffusion barrier comprises a nitride alloy of a material of the intrinsic layer.
10. The apparatus of claim 9 , wherein the material of the intrinsic layer comprises a group III-V compound semiconductor material.
11. The apparatus of claim 10 , wherein the intrinsic layer comprises indium gallium arsenide (InGaAs) and the diffusion barrier comprises InGaAs 1-y N y , wherein y is less than 0.03.
12. The apparatus of claim 10 , wherein the source material and the drain material comprise a group III-V compound semiconductor material.
13. The apparatus of claim 9 , wherein the diffusion barrier comprises a pseudomorphic layer.
14. A method comprising:
defining an area of an intrinsic layer on a substrate for a channel of a transistor device and a source and a drain of the transistor device;
forming a diffusion barrier layer in an area defined for a source and in an area defined for the drain, the diffusion barrier layer comprising nitrogen and having a conduction band energy that is less than a conduction band energy of the channel and higher than a conduction band energy of one of the source material and the drain material; and
forming a source on the diffusion barrier layer in the area defined for the source and forming a drain in the area defined for the drain.
15. The method of claim 14 , wherein the intrinsic layer comprises a group III-V compound semiconductor material.
16. The method of claim 15 , wherein the diffusion barrier layer comprises a nitride alloy of the group III-V compound semiconductor of the intrinsic layer.
17. The method of claim 15 , wherein the intrinsic layer comprises indium gallium arsenide (InGaAs) and the diffusion barrier comprises InGaAs 1-y N y , wherein y is less than 0.03.
18. The method of claim 14 , wherein forming the diffusion barrier comprises forming a pseudomorphic layer.
19. The method of claim 14 , further comprising forming a gate stack on the channel, the gate stack comprising a gate dielectric and a gate electrode wherein the gate dielectric is disposed between the channel and the gate electrode.
20. The method of claim 19 , wherein forming a source and a drain comprise forming an N-type source and an N-type drain.
21. An apparatus comprising:
a substrate;
a transistor device on the substrate comprising:
an intrinsic layer comprising a channel;
a source material on a first side of the channel and a drain material on a second side of the channel; and
a diffusion barrier between the intrinsic layer and each of the source material and the drain material, the diffusion barrier comprising a conduction band energy that is less than a conduction band energy of the channel and higher than a conduction band energy of the source material or the drain material, wherein the diffusion barrier comprises a pseudomorphic layer.