Techniques for increasing channel region tensile strain in n-MOS devices
Techniques are disclosed for forming increasing channel region tensile strain in n-MOS devices. In some cases, increased channel region tensile strain can be achieved via S/D material engineering that deliberately introduces dislocations in one or both of the S/D regions to produce tensile strain in the adjacent channel region. In some such cases, the S/D material engineering to create desired dislocations may include using a lattice mismatched epitaxial S/D film adjacent to the channel region. Numerous material schemes for achieving multiple dislocations in one or both S/D regions will be apparent in light of this disclosure. In some cases, a cap layer can be formed on an S/D region to reduce contact resistance, such that the cap layer is an intervening layer between the S/D region and S/D contact. The cap layer includes different material than the underlying S/D region and/or a higher dopant concentration to reduce contact resistance.
1. An integrated circuit, comprising:
a monocrystalline region;
a gate structure above a portion of the monocrystalline region;
a source or drain region in the monocrystalline region at a side of the gate structure, the source or drain region including a first semiconductor material, a dopant, and multiple dislocations;
a contact structure over the source or drain region; and
an intervening layer between the source or drain region and the contact structure, the intervening layer including
a higher dopant concentration than the source or drain region.
2. The integrated circuit of claim 1 , wherein the multiple dislocations include at least four dislocations.
3. The integrated circuit of claim 1 , wherein the portion of the monocrystalline region under the gate structure and adjacent the source or drain region includes tensile strain.
4. The integrated circuit of claim 3 , wherein average tensile strain in the channel region is at least 0.2 percent.
5. The integrated circuit of claim 1 , wherein the source or drain region has a greater than 3 percent lattice mismatch with respect to the monocrystalline region.
6. The integrated circuit of claim 1 , wherein the higher dopant concentration of the intervening layer includes a higher concentration of n-type dopant than the source or drain region.
7. The integrated circuit of claim 1 , wherein an upper portion of the source or drain region includes an n-type dopant in a concentration of greater than 1E18 atoms per cubic centimeter.
8. The integrated circuit of claim 1 , wherein the monocrystalline region includes silicon, and the source or drain region includes silicon and germanium and has a germanium concentration of at least 30 percent.
9. The integrated circuit of claim 1 , wherein the source or drain region includes a germanium concentration that is at least 30 percent more than the monocrystalline region.
10. The integrated circuit of claim 9 , wherein:
the intervening layer includes silicon; and
the higher dopant concentration of the intervening layer includes a higher concentration of n-type dopant than the source or drain region.
11. The integrated circuit of claim 1 , wherein the monocrystalline region includes indium gallium arsenide, and the source or drain region includes indium gallium arsenide.
12. The integrated circuit of claim 1 , wherein the source or drain region includes at least 27 percent more indium than the monocrystalline region.
13. The integrated circuit of claim 1 , wherein the monocrystalline region includes a fin structure, and the gate structure is on multiple sides of the fin structure.
14. The integrated circuit of claim 1 , wherein the monocrystalline region includes a nanowire or nanoribbon, and the gate structure wraps around the nanowire or nanoribbon.
15. An integrated circuit comprising:
a monocrystalline region including a first semiconductor material;
a gate structure above a portion of the monocrystalline region;
a source or drain region in the monocrystalline region and adjacent to the portion of the monocrystalline region under the gate structure, the source or drain region including a second semiconductor material that is doped n-type and has a greater than 2 percent lattice mismatch with respect to the first semiconductor material;
a contact structure over the source or drain region; and
an intervening layer between the source or drain region and the contact structure, the intervening layer including
a higher dopant concentration than the source or drain region, and/or
a semiconductor material different than the second semiconductor material.
16. The integrated circuit of claim 15 , wherein the portion of the monocrystalline region under the gate structure and adjacent the source or drain region includes tensile strain.
17. The integrated circuit of claim 15 , wherein the higher dopant concentration of the intervening layer includes a higher concentration of n-type dopant than the source or drain region.
18. An integrated circuit, comprising:
a monocrystalline region of silicon;
a gate structure above a portion of the monocrystalline region;
a source or drain region in the monocrystalline region at a side of the gate structure, the source or drain region including germanium at a concentration in excess of 30 percent, such that the portion of the monocrystalline region of silicon under the gate structure includes tensile strain;
a contact structure over the source or drain region; and
an intervening layer between the source or drain region and the contact structure, the intervening layer including
a higher dopant concentration than the source or drain region.
19. The integrated circuit of claim 18 , wherein the higher dopant concentration of the intervening layer includes a higher concentration of n-type dopant than the source or drain region.
20. The integrated circuit of claim 18 , wherein:
the intervening layer includes silicon; and
the higher dopant concentration of the intervening layer includes a higher concentration of n-type dopant than the source or drain region.