Method of forming programmable anti-fuse element
View Patent ↗A programmable anti-fuse element includes a substrate ( 224 ), an N-well ( 426 ) in the substrate, an electrically insulating layer ( 427 ) over the N-well, and a gate electrode ( 430 ) over the electrically insulating layer. The gate electrode has n-type doping so that the N-well is able to substantially contain within its boundaries a current generated following a programming event of the programmable anti-fuse element. In the same or another embodiment, a twice-programmable fuse element ( 100 ) includes a metal gate fuse ( 110 ) and an oxide anti-fuse ( 120 ) such as the programmable anti-fuse element just described.
1. A method of forming a programmable element comprising forming an anti-fuse transistor that is part of the programmable element, forming the transistor comprising:
providing a semiconductor substrate including an N-well therein;
providing a gate insulating layer over the substrate;
providing a metal gate over the gate insulating layer including providing n-type doping of the gate;
wherein the gate insulating layer is adapted to undergo a breakdown yielding a short between the gate and the N-well in the substrate in response to a first electric current applied to the gate;
wherein the gate is adapted to undergo voiding yielding an open circuit in response to a second electric current applied to the gate, the second electric current being larger than the first electric current; and
wherein an electrical resistance of the programmable element after voiding is greater than an electrical resistance of the programmable element after breakdown.
2. The method of claim 1 , wherein the gate insulating layer comprises an oxide.
3. The method of claim 1 , wherein the gate insulating layer comprises a high-k material.
4. The method of claim 1 , wherein:
forming the programmable element comprises forming a plurality of identical programmable elements;
providing the N-well comprises providing one of respective N-wells for respective ones of the programmable elements and a common N-well for all of the programmable elements.
5. The method of claim 1 , further comprising:
providing a source region and a drain region for the gate electrode;
providing an electrical short between the source region and the drain region.
6. The method of claim 1 , wherein an electrical resistance of the programmable element after the breakdown is approximately four orders of magnitude lower than an electrical resistance of the programmable element before the breakdown.
7. The method of claim 1 , wherein the electrical resistance of the programmable element after voiding is 10 to 100 times higher than an electrical resistance of the programmable element after breakdown.
8. The method of claim 1 , further comprising providing a sense amplifier coupled to the N-well to receive a post-breakdown current contained within the N-well and to compare the post-breakdown current with a reference current.