Ferroelectric based memory cell with non-volatile retention
View Patent ↗Described is an apparatus which comprises: a first access transistor controllable by a write word-line (WWL); a second access transistor controllable by a read word-line (RWL); and a ferroelectric cell coupled to the first and second access transistors, wherein the ferroelectric cell is programmable via the WWL and readable via the RWL. Described is a method which comprises: driving a WWL, coupled to a gate terminal of a first access transistor, to cause the first access transistor to turn on; and driving a WBL coupled to a source/drain terminal of the first access transistor, the driven WBL to charge or discharge a storage node coupled to the first access transistor when the first access transistor is turned on, wherein the ferroelectric cell is coupled to the storage node and programmable according to the charged or discharged storage node.
1. An apparatus comprising:
a first access device controllable by a write word-line (WWL);
a second access device controllable by a read word-line (RWL); and
a cell comprising ferroelectric material, wherein the cell is coupled to the first and second access devices, and wherein the cell is programmable via the WWL and readable via the RWL,
wherein the cell includes a device having a gate terminal, which includes a capacitor comprising ferroelectric material, wherein the device has a source and a drain terminal, and wherein if the device is an n-type device then one of the source or drain terminal is connected to a ground node, otherwise if the device is a p-type device then the source or drain terminal is connected to a power supply node.
2. The apparatus of claim 1 , wherein the capacitor is programmable via the WWL.
3. The apparatus of claim 1 , wherein the capacitor is integrated within the gate terminal of the device of the cell.
4. The apparatus of claim 1 , wherein the capacitor is coupled in series with the first access device.
5. The apparatus of claim 1 , wherein the capacitor is coupled to the first access device and a node to provide a read-assist signal.
6. The apparatus of claim 1 , wherein the first access device, the second access device, and the cell comprise the ferroelectric material.
7. The apparatus of claim 1 , wherein the first access device includes:
one of a source or drain terminal coupled to a write bit-line (WBL); and
one of a source or drain terminal coupled to the cell.
8. The apparatus of claim 1 , wherein the second access device includes:
one of a source or drain terminal coupled to a read bit-line (RBL); and
one of a source or drain terminal coupled to the cell.
9. A method comprising:
driving a write word-line (WWL), coupled to a gate terminal of a first access transistor, to cause the first access transistor to turn on;
driving a write bit-line (WBL), coupled to one of a source or drain terminal of the first access transistor, the driven WBL to charge or discharge a storage node coupled to the first access transistor when the first access transistor is turned on; and
programming a logic state in a ferroelectric cell according to the charged or discharged storage node,
wherein the ferroelectric cell includes a device having a gate terminal which includes a capacitor comprising ferroelectric material, wherein the device has a source and a drain terminal, and wherein if the device is an n-type device then one of the source or drain terminal is connected to a ground node, otherwise if the device is a p-type device then the source or drain terminal is connected to a supply node.
10. The method of claim 9 , wherein the ferroelectric cell is coupled to the storage node.
11. The method of claim 9 , wherein programming the logic state in the ferroelectric cell comprises:
driving the WBL and WWL for a suitable duration to charge or discharge the storage node;
turning off the first access transistor; and
switching a ferroelectric material of the ferroelectric cell according to the charged or discharged storage node.
12. The method of claim 9 comprises driving a read word-line (RWL), coupled to a gate terminal of a second access transistor, to cause a second access transistor to turn off when the first access transistor is turned on, wherein the second access transistor is coupled to the ferroelectric cell.
13. The method of claim 12 comprises:
driving the WWL to cause the first access transistor to turn off;
driving the RWL to cause the second access transistor to turn on; and
sensing a read bit-line (RBL), coupled to the second access transistor, to determine a logic state programmed in the ferroelectric cell.
14. The method of claim 12 comprises:
driving the WWL to cause the first access transistor to turn off;
driving the RWL to cause the second access transistor to turn on; and
sensing a read bit-line (RBL), coupled to the second access transistor, to determine a logic state stored in the storage node.
15. A system comprising:
a processor;
a memory coupled to the processor, the memory including:
a first access device controllable by a write word-line (WWL);
a second access device controllable by a read word-line (RWL); and
a cell coupled to the first and second access devices, wherein the cell comprises a ferroelectric material, wherein the cell is programmable via the WWL and readable from via the RWL, wherein the cell includes a device having a gate terminal which includes a capacitor comprising ferroelectric material, wherein the device has a source and a drain terminal, and wherein if the device is an n-type device then one of the source or drain terminal is connected to a ground node when the device is an n-type device, otherwise if the device is a p-type device then one of the source or drain terminal is connected to a supply node when the device is a p-type device; and
a wireless interface to allow the processor to communicate with another device.
16. The system of claim 15 , wherein the device includes a transistor.
17. The system of claim 15 , wherein the capacitor is programmable via the WWL.
18. The system of claim 15 , wherein the capacitor is integrated within the gate terminal of the transistor of the cell.
19. The system of claim 15 , wherein the capacitor is coupled in series with the first access transistor.
20. An apparatus comprising:
a first access device controllable by a write word-line (WWL);
a second access device controllable by a read word-line (RWL); and
a cell comprising ferroelectric material, wherein the cell is coupled to the first and second access devices, and wherein the cell is programmable via the WWL and readable via the RWL,
wherein the cell includes:
a gate including a capacitor comprising ferroelectric material, wherein the capacitor is coupled to a read assist line;
an n-type device having a gate terminal coupled to the gate, wherein the device has a source and a drain terminal, wherein the source terminal is connected to a ground node, and wherein the drain terminal is connected to the second access device.
21. The apparatus of claim 20 , wherein the first and second access devices are n-type devices.