Germanium-based quantum well devices
View Patent ↗A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.
1. A device, comprising:
a lower barrier region comprising a large band gap material;
a quantum well channel region comprising germanium on the lower barrier region;
an upper barrier region comprising a large band gap material on the quantum well region;
a spacer region on the quantum well channel region;
an etch stop region on the spacer region, the etch stop region comprising silicon and being substantially free from germanium;
a gate dielectric on the etch stop region;
a gate electrode on the gate dielectric; and
a first contact stack to one side of the gate electrode, and on the lower barrier region, spacer region, and etch stop region, the first contact stack comprising:
an upper spacer region comprising silicon germanium on the etch stop region;
a doped region on the upper spacer region, the doped region comprising silicon germanium doped with boron;
wherein the upper barrier region is part of the first contact stack; and
a contact region on the upper barrier region.
2. The device of claim 1 , wherein the spacer region comprises silicon germanium.
3. The device of claim 1 , wherein the gate dielectric is directly on the etch stop region.
4. The device of claim 1 , wherein the etch stop region comprises a first portion comprising silicon and a second portion on the first portion.
5. The device of claim 4 , wherein the second portion comprises silicon dioxide.
6. The device of claim 5 , wherein the gate dielectric is directly on the second portion of the etch stop region.
7. The device of claim 1 , wherein the etch stop region has a thickness of less than twenty angstroms.
8. The device of claim 1 , wherein the upper barrier region comprises silicon germanium.
9. The device of claim 8 , wherein the lower barrier region comprises silicon germanium.
10. The device of claim 1 , further comprising:
a doped region on the lower barrier region, the doped region comprising silicon germanium doped with boron; and
a lower spacer region comprising silicon germanium on the doped region and under the quantum well channel region.
11. The device of claim 1 , wherein the lower barrier region and the upper barrier region each comprises silicon germanium.
12. The device of claim 1 , wherein the lower barrier region comprises a group III-V material.
13. The device of claim 12 , wherein the lower barrier region comprises GaAs.
14. The device of claim 12 , wherein the upper barrier region comprises a group III-V material.
15. The device of claim 1 , wherein both a region directly above the quantum well channel region and a region directly below the quantum well channel region comprise silicon germanium, with a higher percentage of silicon further from the quantum well channel region and a lower percentage of silicon closer to the quantum well channel region.
16. The device of claim 15 , wherein the lower barrier region is the region directly below the quantum well channel region.
17. The device of claim 15 , wherein the spacer region is the region directly above the quantum well channel region.
18. The device of claim 1 , wherein the gate dielectric comprises a first dielectric region having a first dielectric constant and a second dielectric region having a second dielectric constant on the first dielectric region, the second dielectric constant being higher than the first dielectric constant.
19. The device of claim 1 , wherein the lower barrier region, quantum well channel region, upper barrier region, spacer region, etch stop region, gate dielectric, and gate electrode are all part of a p-type transistor, and further comprises an n-type transistor, the n-type transistor comprising:
a lower barrier region comprising a group III-V material;
a quantum well channel region comprising a group III-V material on the lower barrier region;
an upper barrier region comprising a group III-V material on the quantum well region;
a gate dielectric on the quantum well channel region and not in contact with the quantum well channel region; and
a gate electrode on the gate dielectric.
20. The device of claim 1 , wherein the lower barrier region, quantum well channel region, upper barrier region, spacer region, etch stop region, gate dielectric, and gate electrode are all part of a p-type transistor, and further comprises an n-type transistor, the n-type transistor comprising:
a source region in a substrate;
a drain region in the substrate, a channel region in the substrate and between the source and drain regions;
a gate dielectric on the channel region and having side walls;
a gate electrode on the gate dielectric and having side walls; and
spacers adjacent the side walls of the gate dielectric and the gate electrode.