IP Library Granted Patent US 7,345,689
Granted Patent B2
US 7,345,689 · App. 10/742,216 · Granted Mar 18, 2008

Interfacing a digital display card through PCI express connector

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Quick Facts
Patent No.
US 7,345,689
App. No.
10/742,216
Granted
Mar 18, 2008
Kind
B2
Abstract

An embodiment of the present invention is a technique to interface a display card through an interface connector. A video output device on the display card generates digital video output signals from a graphics chipset on a motherboard. The card is plugged into an interface connector on the motherboard. The interface connector is compatible with a first interface standard. The video output device is compatible to a second interface standard. A card detector is coupled to the video output device and the interface connector to enable the video output device if the graphics chip set supports the video output device.

Claims (36)

1. An apparatus comprising:

a video output device on a card to generate digital video output signals from a graphics chipset on a motherboard, the card being plugged into an interface connector on the motherboard, the interface connector being compatible with a first interface standard, the video output device being compatible to a second interface standard; and

a card detector coupled to the video output device and the interface connector to enable the video output device if the graphics chipset supports the video output device.

2. The apparatus of claim 1 wherein the card detector comprises:

a strapping mechanism to pull a strapping point to a logic level when the graphics chipset is present on the motherboard.

3. The apparatus of claim 1 further comprising:

a digital display device compatible with the video output device to drive a display monitor using the digital video output signals.

4. The apparatus of claim 1 wherein the first interface standard is compatible with a peripheral component interconnect (PCI) Express standard.

5. The apparatus of claim 1 wherein the second interface standard is compatible with a serial digital video output (SDVO) standard.

6. The apparatus of claim 1 wherein the graphics chipset is an integrated graphics memory controller hub (GMCH) chipset.

7. The apparatus of claim 3 wherein the digital display device is a digital display codec device supporting at least one of a National Television System Committee (NTSC) format, a phase alternation by line (PAL) format, a sequential technique and memory storage (SECAM) format, and a high definition television (HDTV) format, a transmission minimized differential signal (TMDS), and a low voltage differential signaling (LVDS) device.

8. A method comprising:

generating digital video output signals from a graphics chipset on a motherboard using a video output device on a card, the card being plugged into an interface connector on the motherboard, the interface connector being compatible with a first interface standard, the video output device being compatible to a second interface standard; and

enabling the video output device by a card detector if the graphics chip set supports the video output device.

9. The method of claim 8 wherein enabling comprises:

pulling a strapping point to a logic level by a strapping mechanism when the graphics chipset is present on the motherboard.

10. The method of claim 8 further comprising:

driving a display monitor using the digital video output signals by a digital display device compatible with the video output device.

11. The method of claim 8 wherein the first interface standard is compatible with a peripheral component interconnect (PCI) Express standard.

12. The method of claim 8 wherein the second interface standard is compatible with a serial digital video output (SDVO) standard.

13. The method of claim 8 wherein the graphics chipset is an integrated graphics memory controller hub (GMCH) chipset.

14. The method of claim 10 wherein the digital display device is one of a digital display codec device supporting at least one of a National Television System Committee (NTSC) format, a phase alternation by line (PAL) format, a sequential technique and memory storage (SECAM) format, and a high definition television (HDTV) format, a transmission minimized differential signal (TMDS), and a low voltage differential signaling (LVDS) device.

15. A system comprising:

a graphics chipset on a motherboard;

an interface connector attached to the motherboard and compatible with a first interface standard; and

a card plugged into the interface connector to drive a display monitor, the card comprising:

a video output device to generate digital video output signals from the graphics chipset, the video output device being compatible to a second interface standard, and

a card detector coupled to the video output device and the interface connector to enable the video output device if the graphics chipset supports the video output device.

16. The system of claim 15 wherein the card detector comprises:

a strapping mechanism to pull a strapping point to a logic level when the graphics chipset is present on the motherboard.

17. The system of claim 15 wherein the card further comprises:

a digital display device compatible with the video output device to drive a display monitor using the digital video output signals.

18. The system of claim 15 wherein the first interface standard is compatible with a peripheral component interconnect (PCI) Express standard.

19. The system of claim 15 wherein the second interface standard is compatible with a serial digital video output (SDVO) standard.

20. The system of claim 15 wherein the graphics chipset is an integrated graphics memory controller hub (GMCH) chipset.

21. The system of claim 18 wherein the digital display device is a digital display codec device supporting at least one of a National Television System Committee (NTSC) format, a phase alternation by line (PAL) format, a sequential technique and memory storage (SECAM) format, and a high definition television (HDTV) format, a transmission minimized differential signal (TMDS), and a low voltage differential signaling (LVDS) device.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 15, 2022
From: INTEL CORPORATION
To: TAHOE RESEARCH, LTD.
Reel/Frame 061175/0176 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 19, 2003
From: JANUS, SCOTT R.; SHAH, KATEN A.; WILEN, ADAM H.
To: INTEL CORPORATION
Reel/Frame 014838/0839 →