Alloyed underlayer for microelectronic interconnects
View Patent ↗Apparatus and methods of fabricating a microelectronic interconnect having an underlayer which acts as both a barrier layer and a seed layer. The underlayer is formed by co-depositing a noble metal and a barrier material, such as a refractory metal, or formed during thermal post-treatment, such as thermal annealing, conducted after two separately depositing the noble metal and the barrier material, which are substantially soluble in one another. The use of a barrier material within the underlayer prevents the electromigration of the interconnect conductive material and the use of noble material within the underlayer allows for the direct plating of the interconnect conductive material.
1. A method of fabricating an interconnect, comprising:
providing at least one dielectric layer;
forming at least one opening extending into said at least one dielectric layer, wherein said opening is defined by at least one side;
sequentially depositing a barrier material and a noble metal at least within said opening;
annealing said barrier material and said noble metal to form an alloyed underlayer; and
plating at least one conductive material to fill said opening and abut said underlayer.
2. The method of claim 1 , wherein depositing said barrier material comprises depositing a refractory metal barrier material.
3. The method of claim 1 , wherein depositing said barrier material comprises depositing a barrier material selected form the group consisting of tantalum, titanium, tungsten, molybdenum, or zirconium.
4. The method of claim 1 , wherein depositing said barrier material comprises depositing a carbided barrier material.
5. The method of claim 1 , wherein depositing said barrier material comprises depositing a nitrided barrier material.
6. The method of claim 1 , wherein depositing said noble metal comprises depositing a noble metal selected from the group consisting of ruthenium, platinum, palladium, rhenium, osmium, iridium, gold, and rhodium.