Efficient low cost on-die configurable bridge controller

1. An apparatus comprising:

an interface comprising a line-state output; and

a state machine to set the line-state output to a value that is one of: a single-ended zero-state (SE0-state) value, a J-state value, or a K-state value,

wherein the state machine has a plurality of states including: a reset state, a full speed-detect state, a low-speed-detect state, a host-drive-SE0 state, a device-response-K state, a device-response-SQ state, a host response-JK state, an idle-done state, and a full-speed-low-speed-reset state;

wherein the state machine has a line-state state that is one of the plurality of states; and

wherein the value of the line-state output is based at least in part upon the line-state state.

2. The apparatus of claim 1 , wherein the interface is a first interface, and the apparatus comprising:

a first translation circuitry to process a transaction received on the first interface and to generate a transaction for a second interface.

3. The apparatus of claim 2 , comprising:

a second translation circuitry to process a transaction received on the second interface and to generate a transaction for the first interface.

4. The apparatus of claim 1 ,

wherein the state machine is to set the line-state output to the SE0-state value when the line-state state is any of: the host-drive-SE0 state, the device-response-SQ state, the idle-done state, or the full-speed-low-speed-reset state;

wherein the state machine is to set the line-state output to the K-state value when the line-state state is any of: the device-response-K state or the low-speed-detect state; and

wherein the state machine is to set the line-state output to the J-state value when the line-state state is the full-speed-detect state.

5. The apparatus of claim 4 , comprising:

a speed-mode input to have a value that is one of: a low-speed value, a full-speed value, or a high-speed value,

wherein, when the line-state state is the reset state, the state machine is to set the line-state output to the J-state value while the speed-mode input has the low-speed value, and otherwise set the line-state output to the K-state value.

6. The apparatus of claim 5 , comprising:

a speed-mode input to have a value that is one of: a low-speed value, a full-speed value, or a high-speed value;

a host data input;

a host transmit-valid input; and

a host op-mode input to have a value that is one of: a normal-operation value, a non-driving value, a disable value, or a normal-operation-without-automatic-generation value,

wherein, when the line-state state is the host-response-JK state, the state machine is to set the line-state output to the K-state value while the host data input has a zero value, the host transmit-valid input is asserted, and the host op-mode input has the disable value, and otherwise set the line-state output to the J-state value.

7. The apparatus of claim 3 , wherein the first interface is a host interface, and wherein the second interface is a first device interface, and the apparatus comprising:

a second device interface; and

a device selection input to have one of: a first value, or a second value,

wherein, when the device selection input has the first value, the first translation circuitry is to process a transaction received on the host interface and to generate a transaction for the first device interface, and the second translation circuitry is to process a transaction received on the first device interface and to generate a transaction for the host interface.

8. The apparatus of claim 3 , wherein the first interface is a host interface, and wherein the second interface is a first device interface, and the apparatus comprising:

a second device interface; and

a device selection input to have one of: a first value, or a second value,

wherein, when the device selection input has the second value, the first translation circuitry is to process a transaction received on the host interface and to generate a transaction for the second device interface, and the second translation circuitry is to process a transaction received on the second device interface and to generate a transaction for the host interface.

9. The apparatus of claim 2 , wherein both the first interface and the second interface comprise a set of USB 2.0 Transceiver Macrocell Interface (UTMI) compliant inputs and outputs.

10. An apparatus comprising:

a host controller;

a device controller; and

a bridge controller coupled to the host controller by a first interface and coupled to the device controller by a second interface, the bridge controller comprising:

a downstream translation circuitry to process a transaction received on the first interface and to generate a transaction for the second interface;

an upstream translation circuitry to process a transaction received on the second interface and to generate a transaction for the first interface; and

a state machine incorporating sequential logic to set a line-state output of the first interface to a value that is one of: a single-ended-zero-state (SE0-state) value, a J-state value, or a K-state value,

wherein the state machine has a plurality of states including: a reset state, a full-speed-detect state, a low-speed-detect state, a host-drive-SE0 state, a device-response-K state, a device-response-SQ state, a host-response-JK state, an idle-done state, and a full-speed-low-speed-reset state;

wherein the state machine has a line-state state that is one of the plurality of states;

wherein the host controller is to generate a transaction for the first interface based at least in part upon the state of the line-state output; and

wherein the device controller is to generate a transaction for the second interface based at least in part upon the state of the line-state output.

11. The apparatus of claim 10 , wherein the device controller is coupled to a device that comprises at least one of: a memory interface, a security engine, or a manageability engine.

12. The apparatus of claim 10 , wherein the first interface is a host interface, and the second interface is a first device interface, and the apparatus comprising:

a second device interface; and

a device selection input to have one of: a first value, or a second value,

wherein the bridge controller is coupled to the second device controller by the second device interface;

wherein, when the device selection input has the first value, the downstream translation circuitry is to process a transaction received on the host interface and to generate a transaction for the first device interface, and the upstream translation circuitry is to process a transaction received on the first device interface and to generate a transaction for the host interface.

13. The apparatus of claim 10 , wherein the first interface is a host interface, and the second interface is a first device interface, and the apparatus comprising:

a second device interface; and

a device selection input to have one of: a first value, or a second value,

wherein the bridge controller is coupled to the second device controller by the second device interface;

wherein, when the device selection input has the second value, the downstream translation circuitry is to process a transaction received on the host interface and to generate a transaction for the second device interface, and the upstream translation circuitry is to process a transaction received on the second device interface and to generate a transaction for the host interface.

14. The apparatus of claim 10 ,

wherein the state machine is to set the line-state output of the first interface to the SEO-state value when the line-state state is any of: the host-drive-SEO state, the device-response-SQ state, the idle-done state, or the full-speed-low-speed-reset state;

wherein the state machine is to set the line-state output of the first interface to the K-state value when the line-state state is any of: the device-response-K state and the low-speed-detect state; and

wherein the state machine is to set the line-state output of the first interface to the J-state value when the line-state state is the full-speed-detect state.

15. The apparatus of claim 14 :

a speed-mode input to have a value that is one of: a low-speed value, a full-speed value, or a high-speed value;

wherein, when the line-state state is the reset state, the state machine is to set the line-state output of the first interface to the J-state value while the speed-mode input has the low-speed value, and otherwise set the line-state output of the first interface to the K-state value.

16. The apparatus of claim 15 , comprising:

a host data input;

a host transmit-valid input; and

a host op-mode input to have a value that is one of: a normal-operation value, a non-driving value, a disable value, or a normal-operation-without-automatic-generation value,

wherein, when the line-state state is the host-response-JK state, the line-state state machine is to set the line-state output of the first interface to the K-state value while the host data input has a zero value, the host transmit-valid input is asserted, and the host op-mode input has the disable value, and otherwise set the line-state output of the first interface to the J-state value.

17. A system comprising a memory, a processor coupled to the memory, a wireless interface for allowing the processor to communicate with another device, and a computing device comprising:

an interface comprising a line-state output; and

a state machine to set the line-state output to a value that is one of: a single-ended-zero state (SE0-state) value, a J-state value, or a K-state value,

wherein the state machine is to have has a plurality of states including: a reset state, a full-speed-detect state, a low-speed-detect state, a host-drive-SE0 state, a device-response-K state, a device-response-SQ state, a host response-JK state, an idle-done state, and a full-speed-low-speed-reset state;

wherein the state machine has a line-state state that is one of the plurality of states; and

wherein the value of the line-state output is based at least in part upon the line-state state.

18. The system of claim 17 , wherein the interface is a first interface, and the computing device comprising:

a second interface;

a device controller coupled to the second interface; and

a service device coupled to the device controller, the service device comprising at least one of: a memory interface, a security engine, or a manageability engine.

19. The system of claim 17 , wherein the interface is a first interface, and the computing device comprising:

a second interface;

wherein both the first interface and the second interface comprise a set of USB 2.0 Transceiver Macrocell Interface (UTMI) compliant inputs and outputs.