Forming a non-planar transistor having a quantum well channel

1. An apparatus comprising:

a substrate;

a buried oxide layer formed directly on the substrate and between the substrate and a semiconductor fin;

the semiconductor fin comprising a silicon on insulator core formed directly on the buried oxide layer, the semiconductor fin providing a channel region for a non-planar field effect transistor (FET);

a first semiconductor layer comprising silicon germanium (SiGe) directly formed on and wrapped around the semiconductor fin, wherein the first semiconductor layer comprises a quantum well layer including a smaller bandgap than a bandgap of the semiconductor fin, the SiGe having a Ge concentration of at least approximately 10%;

a second semiconductor layer comprising tensile strained silicon directly wrapped around and on the first semiconductor layer; and a dielectric layer adjacent the second semiconductor layer;

wherein the first semiconductor layer provides a quantum well for holes; and wherein the second semiconductor layer provides a quantum well for electrons.

2. The apparatus of claim 1 , wherein the semiconductor fin comprises silicon.

3. The apparatus of claim 1 , further comprising a gate electrode adjacent the dielectric layer.

4. The apparatus of claim 3 , wherein the apparatus comprises a non-planar metal oxide semiconductor field effect transistor (MOSFET).

5. The apparatus of claim 1 , wherein the first semiconductor layer comprises a compressive strained quantum well layer.

6. The apparatus of claim 1 , wherein the apparatus comprises one of a high electron mobility transistor and a high hole mobility transistor.

7. An apparatus comprising:

a substrate;

a buried oxide layer directly formed on the substrate;

a semiconductor fin directly formed on the buried oxide layer, the semiconductor fin comprising a silicon on insulator core and providing a channel region for a non-planar field effect transistor (FET);

a first semiconductor layer comprising silicon germanium (SiGe) directly formed on and wrapped around the semiconductor fin, wherein the first semiconductor layer comprises a quantum well layer including a smaller bandgap than a bandgap of the semiconductor fin, the SiGe having a Ge concentration of at least approximately 10%;

a second semiconductor layer comprising tensile strained silicon directly wrapped around and on the first semiconductor layer, wherein the second semiconductor layer includes a smaller bandgap than the bandgap of the semiconductor fin and a larger bandgap than the bandgap of the first semiconductor layer; and

a dielectric layer adjacent the second semiconductor layer;

wherein the first semiconductor layer provides a quantum well for holes; and wherein the second semiconductor layer provides a quantum well for electrons.

8. The apparatus of claim 7 , wherein the first semiconductor layer is compressive strained.

9. The apparatus of claim 7 , wherein the semiconductor fin comprises silicon.

10. The apparatus of claim 7 , further comprising a gate electrode adjacent the dielectric layer.

11. The apparatus of claim 10 , further comprising a contact layer adjacent to the gate electrode.

12. The apparatus of claim 7 , wherein the semiconductor fin is strained.