IP Library Granted Patent US 7,020,818
Granted Patent B2
US 7,020,818 · App. 10/796,353 · Granted Mar 28, 2006

Method and apparatus for PVT controller for programmable on die termination

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Quick Facts
Patent No.
US 7,020,818
App. No.
10/796,353
Granted
Mar 28, 2006
Kind
B2
Abstract

Embodiments include an on die termination circuit. The on die termination circuit may be programmable. The on die termination circuit may be programmed to compensate for environmental conditions and the physical characteristics of the device. The programmed on die termination circuit allows for faster transfer rates over communication lines by reducing the time needed to recover from signal reflection and similar issues.

Claims (31)

1. An apparatus comprising:

a test block to determine a condition on a chip;

an encoder to encode the condition to a first encoded condition;

a conversion circuit to convert the first encoded condition into an approximated second encoding; and

a compensation circuit to adjust an on die termination circuit based on the approximated second encoding.

2. The apparatus of claim 1 , further comprising:

a receiving circuit to receive an incoming signal, the receiving circuit to receive a third encoded condition and compensate the termination of the signal for the condition.

3. A system comprising:

a processor;

a first bus coupled to the processor;

a memory device;

a second bus coupled to the memory device;

a memory controller coupled to the first and second buses, the memory controller having a programmable on die termination circuit, a conversion circuit to convert a first encoded signal representing a condition in the memory into an approximated second encoding to program the on die termination circuit.

4. The system of claim 3 , wherein the memory controller can receive data over the second bus at a rate between 200 and 400 megatranfers per second (MTS).

5. The system of claim 3 , wherein the memory controller further comprises the testing circuit to determine the condition in the memory controller and generate the first encoded signal representing the condition.

6. A method comprising:

detecting a condition in a device;

generating an encoded signal representing the condition;

converting the encoded signal into a truncated condition code to program the on die termination circuit; and

programming an on die termination circuit to compensate for the condition.

7. The method of claim 6 , further comprising:

receiving an external signal at a rate of 200 to 400 mega transfers per second (MTS) at the on die termination circuit; and

terminating the external signal.

8. A device comprising:

means for detecting a condition in a device;

means for generating an encoded signal based on the condition;

means for converting the encoded signal into a truncated condition code to program the on die termination circuit; and

means for programming an on die termination circuit based on the encoded signal.

9. The device of claim 8 , further comprising:

means for receiving an external signal at a rate of 200 to 400 mega transfers per second (MTS) at the on die termination circuit; and

means for terminating the external signal.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 15, 2022
From: INTEL CORPORATION
To: TAHOE RESEARCH, LTD.
Reel/Frame 061175/0176 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 8, 2004
From: DOUR, NAVNEET; CHENG, ROGER K.
To: INTEL CORPORATION
Reel/Frame 015064/0258 →