Load mechanism

1. A method comprising:

scheduling a load operation having a size larger than a size of a maximum access supported by a memory device; and

executing the load operation as a plurality of separate load operation segments having a size equivalent to or smaller than the maximum access supported by the memory device.

2. The method of claim 1 wherein executing each of the plurality of load operation segments comprises:

computing a first address associated with a first segment of the plurality of load operation segments;

writing the first address into a first load buffer;

computing a second address associated with a second segment of the plurality of load operation segments; and

writing the second address into a second load buffer.

3. The method of claim 2 further comprising:

executing a memory access using the first address; and

executing a memory access using the second address.

4. The method of claim 3 wherein execution of data corresponding to the first segment and data corresponding to the second segment may complete in any order.

5. The method of claim 4 further comprising tracking the status of the second segment after execution of the first segment has been completed at a vector tracking register (VTR).

6. The method of claim 2 further comprising:

detecting that the first address is an unaligned address; and

allocating a vector split register (VSR).

7. The method of claim 6 further comprising:

storing a first component of the first address located in a first memory address range in the VSR; and

rescheduling the first segment.

8. The method of claim 7 further comprising:

incrementing to a second memory address range; and

merging a second component of the first address located in the second memory address range with the first component in the VSR.

9. The method of claim 8 further comprising rotating the first component and the second component in the VSR.

10. A computer system comprising:

a memory device, and

a central processing unit (CPU) having:

a reservation station (RS) to schedule load operations having a size larger than a size of a maximum access supported by the memory device; and

a Memory Execution Unit (MEU) to execute the load operations as a plurality of separate load operation segments having a size equivalent to or smaller than the maximum access supported by the memory device.

11. The computer system of claim 10 further comprising a decoder to receive an instruction and decode the instruction into one or more load micro operations each having a data type size equal to or smaller than the data type size of the instruction.

12. The computer system of claim 11 further comprising an address generation unit (AGU) to compute addresses for the load operations.

13. The computer system of claim 12 wherein the AGU computes a first address associated with a first segment of the plurality of load operation segments, writes the first address into a first load buffer, computes a second address associated with a second segment of the plurality of load operation segments and writes the second address into a second load buffer.

14. The computer system of claim 13 wherein the MEU executes a memory access using the first address and executes a memory access using the second address.

15. The computer system of claim 14 further comprising a vector tracking register (VTR) to track the status of the second segment after execution of the first segment has been completed.

16. The computer system of claim 10 wherein a data type size of the memory device is one half the data type size of the RS and the AGU.

17. The computer system of claim 13 wherein the AGU includes a vector split register (VSR), wherein the AGU detects that the first address is an unaligned address and allocates the first address to the VSR.

18. An article of manufacture including one or more computer readable media that embody a program of instructions, wherein the program of instructions, when executed by a processing unit, causes the processing unit to perform the process of:

scheduling a load operation having a size larger than a size of a maximum access supported by a memory device; and

executing the load operation as a plurality of separate load operation segments having a sire equivalent to or smaller than the maximum access supported by the memory device.

19. The article of manufacture of claim 18 wherein the program of instructions, when executed by a processing unit, further causes the processing unit to perform the process of:

computing a first address associated with a first segment of the plurality of load operation segments;

writing the first address into a first load buffer;

computing a second address associated with a second segment of the plurality of load operation segments; and

writing the second address into a second load buffer.

20. The article of manufacture of claim 19 wherein the program of instructions, when executed by a processing unit, further causes the processing unit to perform the process of:

executing a memory access using the first address; and

executing a memory access using the second address.

21. The article of manufacture of claim 19 wherein the program of instructions, when executed by a processing unit, further causes the processing unit to perform the process of:

detecting that the first address is an unaligned address; and

allocating a vector split register (VSR).

22. The article of manufacture of claim 21 wherein the program of instructions, when executed by a processing unit, further causes the processing unit to perform the process of:

storing a first component of the first address located in a first memory address range in the VSR; and

rescheduling the first segment.

23. A central processing unit (CPU) comprising:

a reservation station (RS) to schedule load operations having a size larger than a size of a maximum access supported by a memory device; and

a Memory Execution Unit (MEU) to execute the load operations as a plurality of separate load operation segments having a size equivalent to or smaller than the maximum access supported by the memory device.

24. The CPU of claim 23 further comprising an address generation unit (AGU) to compute addresses for the load operations.

25. The CPU of claim 24 wherein the AGU computes a first address associated with a first segment of the plurality of load operation segments, writes the first address into a first load buffer, computes a second address associated with a second segment of the plurality of load operation segments and writes the second address into a second load buffer.