IP Library Granted Patent US 8,458,412
Granted Patent B2
US 8,458,412 · App. 13/168,171 · Granted Jun 4, 2013

Transaction based shared data operations in a multiprocessor environment

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Quick Facts
Patent No.
US 8,458,412
App. No.
13/168,171
Granted
Jun 4, 2013
Kind
B2
Abstract

The apparatus and method described herein are for handling shared memory accesses between multiple processors utilizing lock-free synchronization through transactional-execution. A transaction demarcated in software is speculatively executed. During execution invalidating remote accesses/requests to addresses loaded from and to be written to shared memory are tracked by a transaction buffer. If an invalidating access is encountered, the transaction is re-executed. After a pre-determined number of times re-executing the transaction, the transaction may be re-executed non-speculatively with locks/semaphores.

Claims (34)

1. An apparatus comprising:

decode logic adapted to recognize and decode a start transaction instruction to start a transaction and a commit transaction instruction to commit the transaction;

execution resources adapted to execute the transaction;

a cache adapted to hold a plurality of cache lines;

first logic adapted to track a plurality of transactionally accessed cache lines of the plurality of cache lines transactionally accessed during execution of the transaction, wherein each of the plurality of cache lines is associated with a pinning field; and

second logic adapted to set each of the pinning fields associated with the plurality of transactionally accessed cache lines accessed during execution of the transaction to a block value, wherein the control logic is further adapted to block snoops to the plurality of transactionally access cache lines during commit of the transaction in response to the decode logic decoding the commit transaction instruction and each of the pinning fields being set to the block value.

2. The apparatus of claim 1 , wherein the first tracking logic is included within the cache, and wherein the second logic includes cache control logic within the cache.

3. The apparatus of claim 1 , wherein the first tracking logic includes a transaction buffer separate from the cache.

4. The apparatus of claim 1 , wherein the second logic is further adapted to block snoops to the plurality of transactionally access cache lines during commit of the transaction comprises the second logic being further adapted to block snoops for a predetermined amount of time after the decode logic decodes the commit transaction instruction and each of the pinning fields is set to the block value.

5. The apparatus of claim 1 , wherein the second logic is further adapted to block snoops to the plurality of transactionally access cache lines during commit of the transaction comprises the second logic being further adapted to block snoops after the decode logic decodes the commit transaction instruction and each of the pinning fields is set to the block value until a commit of the transaction is complete.

6. The apparatus of claim 5 , wherein until a commit of the transaction is complete comprises when the commit transaction instruction is retired.

7. A system comprising:

a processor including:

decode logic adapted to recognize and decode a start transaction instruction to start a transaction and a commit transaction instruction to commit the transaction;

execution resources adapted to execute the transaction;

a cache adapted to hold a plurality of cache lines;

a tracking mechanism adapted to track a plurality of transactionally accessed cache lines of the plurality of cache lines transactionally accessed during execution of the transaction, wherein each of the plurality of cache lines is associated with a pinning field; and

control logic adapted to set each of the pinning fields associated with the plurality of transactionally accessed cache lines accessed during execution of the transaction to a block value, wherein the control logic is further adapted to block snoops to the plurality of transactionally access cache lines during commit of the transaction in response to the decode logic decoding the commit transaction instruction and each of the pinning fields being set to the block value; and

a memory coupled to the processor, the memory adapted to hold data loaded into the cache.

8. The system of claim 7 , wherein the tracking mechanism is included within the cache, and wherein the control logic includes cache control logic within the cache.

9. The system of claim 7 , wherein the tracking mechanism includes a transaction buffer separate from the cache.

10. The system of claim 7 , wherein the control logic is further adapted to block snoops to the plurality of transactionally access cache lines during commit of the transaction comprises the control logic being further adapted to block snoops for a predetermined amount of time after the decode logic decodes the commit transaction instruction and each of the pinning fields is set to the block value.

11. The system of claim 7 , wherein the control logic is further adapted to block snoops to the plurality of transactionally access cache lines during commit of the transaction comprises the control logic being further adapted to block snoops after the decode logic decodes the commit transaction instruction and each of the pinning fields is set to the block value until a commit of the transaction is complete.

12. The system of claim 11 , wherein until a commit of the transaction is complete comprises when the commit transaction instruction is retired.

13. A method comprising:

decoding a start transaction instruction with decode logic in a process to start a transaction;

executing the transaction;

tracking a plurality of transactionally accessed cache lines within a cache of the processor transactionally accessed during execution of the transaction, wherein each of the plurality of cache lines is associated with a pinning field; and

decoding a commit transaction instruction with the decode logic to commit the transaction;

setting each of the pinning fields associated with the plurality of transactionally accessed cache lines accessed during execution of the transaction to a block value; and

blocking snoops to the plurality of transactionally accessed cache lines during commit of the transaction in response to decoding the commit transaction instruction and setting each of the pinning fields being to the block value.

14. The method of claim 13 , wherein blocking snoops to the plurality of transactionally accessed cache lines during commit of the transaction comprises blocking snoops for a predetermined amount of time after decoding the commit transaction instruction and setting each of the pinning fields to the block value.

15. The method of claim 13 , wherein blocking snoops to the plurality of transactionally accessed cache lines during commit of the transaction comprises blocking snoops after the decoding the commit transaction instruction and setting the pinning fields to the block value until a commit of the transaction is complete.

16. The method of claim 15 , wherein until a commit of the transaction is complete comprises when the commit transaction instruction is retired.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 15, 2022
From: INTEL CORPORATION
To: TAHOE RESEARCH, LTD.
Reel/Frame 061175/0176 →