IP Library Granted Patent US 8,867,609
Granted Patent B2
US 8,867,609 · App. 13/478,800 · Granted Oct 21, 2014

Dynamically configuring a video decoder cache for motion compensation

Inventor: Rahul Saxena (Sunnyvale, CA)
Assignee: Intel Corporation
H04N19/00509G09G5/39G09G2310/0224G09G2320/0261H04N19/00533G09G2360/121H04N19/00587
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Quick Facts
Patent No.
US 8,867,609
App. No.
13/478,800
Granted
Oct 21, 2014
Kind
B2
Abstract

A video decoder cache used for motion compensation data may be dynamically reconfigured. In some embodiments, it may be reconfigured on picture or frame boundaries and in other embodiments it can be reconfigured on sequence boundaries. The cache may be flushed on each boundary to enable such reconfiguration.

Claims (19)

1. A method comprising:

detecting a type of motion compensation data that is to be processed by a video decoder;

based on the detected type of data, selecting between sequence and frame boundaries on which to reconfigure a video decoder cache, wherein a sequence is more than one consecutive frame; and

reconfiguring the video decoder cache on the selected boundary.

2. The method of claim 1 wherein detecting the type of data includes detecting whether the data is interlaced or progressive.

3. The method of claim 2 including receiving information from a packetized elementary stream parser to determine the type of data.

4. The method of claim 1 wherein said cache is reconfigured to store data from successive adjacent lines of scanned data.

5. The method of claim 3 wherein said cache is configured to receive successive even lines in one cache line and successive odd lines in another cache line.

6. The method of claim 1 including receiving an indication of a block position and whether the block is interlaced or progressive scanned and outputting an indication of tag random access memory address bits in the form of lower order column and lower order row bits.

7. The method of claim 6 including using said lower order column and lower order row bits to access a tag random access memory, receiving from the tag random access memory the higher order row and column bits and comparing those bits to the received address of a data access.

8. The method of claim 7 including receiving a field select bit and using said field select bit to identify a location within a tag random access memory.

9. The method of claim 1 including reconfiguring the video decoder cache depending on whether motion compensation data refers to both fields of a frame of scanned data or only one field of said frame.

10. The method of claim 1 including flushing said cache in connection with reconfiguring said cache.

11. A system comprising:

a cache; and

a configuration unit coupled to said cache, said configuration unit to detect a type of motion compensation data to be processed and to reconfigure a video decoder cache on either frame or sequence boundaries, depending on which type of data is to be processed, wherein a sequence is more than one consecutive frame and to reconfigure the video decoder cache on the selected boundary.

12. The system of claim 11 , said unit to detect whether data to be stored in the cache is interlaced or progressive scanned data and to reconfigure the cache depending on whether the data is interlaced or progressive scanned.

13. The system of claim 11 wherein said configuration unit to reconfigure the cache depending on whether motion compensation data refers to both fields of a frame of scanned data or only one field of said frame.

14. The system of claim 11 , said cache including a tag random access memory storing information about the higher row and column address bits of motion data and being indexed by lower row and column address bits, said tag random access memory including a comparator to compare information about higher row and column address bits with the information from the tag random access memory to determine whether data is cached in said cache.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 15, 2022
From: INTEL CORPORATION
To: TAHOE RESEARCH, LTD.
Reel/Frame 061175/0176 →
Continuity (3)
Continuation 13042638 · Mar 8, 2011
Continuation 11231077 · Sep 20, 2005
Related Publication 20120243610A1 · Sep 27, 2012