Methods and apparatuses for flushing write-combined data from a buffer

1. A method comprising:

write-combining an outbound write transaction intended for transfer of associated data from system memory to an input/output (I/O) device by storing the associated data within a write-combinable buffer, the write-combinable buffer assigned to a range of addresses within a memory address space that is mapped to the I/O device in a memory-mapped Input/Output (MMIO) fashion, the range of addresses being a write-combinable range of addresses that include a set of one or more write-combining windows, each representing a contiguous address space within the range of addresses, and wherein each of the set of write-combining windows is established by a first write operation that falls within the range of addresses that is aligned on cache line boundaries, wherein said write-combinable buffer is a component integrated in a memory controller;

detecting a doorbell register flush request for the I/O device within the memory address space mapped to the I/O device, wherein, the I/O device's device driver software directs the flushing of the write-combinable buffer by initiating the flush request;

identifying the buffer based on the flush request's location within the memory address space mapped to the I/O device; and

flushing the data contents of the buffer to the I/O.

2. The method of claim 1 further comprising:

performing the write combining in response to the transaction address associated with the flush request falling within a write-combinable range of addresses assigned to the I/O device.

3. The method of claim 2 , wherein the data contents of the write-combinable buffer are flushed to the I/O device and the transaction data is stored within the write-combinable buffer if an address range associated with an open write-combining window corresponds to the transaction address of the write transaction, and the transaction address falls within the data address within the assigned write-combining buffer.

4. The method of claim 3 , wherein a set of one or more write-combinable buffers of said memory controller are flushed in linearly increasing order toward said I/O hub.

5. The method of claim 4 , wherein each of the set of write-combining windows is re-established during subsequent write operations that fall within the write-combinable range, but fall outside a previous write-combining window within the write-combinable range.

6. The method of claim 1 wherein the transaction is a write transaction.

7. The method of claim 6 , wherein multiple write-combinable ranges may be established within the MMIO address space mapped to the I/O device.

8. A semiconductor chip, comprising:

a memory controller having an interface to a system memory and a write-combinable buffer, said memory controller also having circuitry to write-combine an outbound write transaction intended for transfer of associated data from the system memory to an input/output (I/O) device by storing the associated data within the write-combinable buffer, the write-combinable buffer assigned to a range of addresses within a memory address space mapped to the I/O device in a memory-mapped input/output (MMIO) fashion, the range of addresses being a write-combinable range of addresses that include a set of one or more write-combining windows, each representing a contiguous address space within the range of addresses, and wherein each of the set of write-combining windows is established by a first write operation that falls within the range of addresses that is aligned on cache line boundaries, the circuitry to also perform the following upon a doorbell register flush request for the I/O device within the memory address space mapped to the I/O device being detected, wherein, the I/O device's device driver software directs the flushing of the write-combinable buffer by initiating the flush request:

identify the buffer based on the flush request's location within the memory address space mapped to the I/O device; and

flush the data contents of the buffer to the I/O device.