IP Library Granted Patent US 10,847,653
Granted Patent B2
US 10,847,653 · App. 15/408,294 · Granted Nov 24, 2020

Semiconductor device having metallic source and drain regions

Inventors: Martin D. Giles (Portland, OR); Annalisa Cappellani (Portland, OR); Sanaz Gardner (Portland, OR); Rafael Rios (Portland, OR); Cory E. Weber (Hillsboro, OR); Aaron A. Budrevich (Portland, OR)
Assignee: Intel Corporation
H01L29/7848H01L21/2225H01L21/2254H01L21/2257H01L21/2258H01L21/28518H01L21/28556H01L21/28593H01L21/3065H01L21/30608H01L21/30617H01L21/823814H01L21/823821H01L27/088H01L27/092H01L29/0847H01L29/165H01L29/167H01L29/401H01L29/456H01L29/66636H01L29/66795H01L29/785H01L29/7839H01L29/7845H01L29/7851H01L29/0673H01L2924/0002
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,847,653
App. No.
15/408,294
Granted
Nov 24, 2020
Kind
B2
Abstract

Semiconductor devices having metallic source and drain regions are described. For example, a semiconductor device includes a gate electrode stack disposed above a semiconducting channel region of a substrate. Metallic source and drain regions are disposed above the substrate, on either side of the semiconducting channel region. Each of the metallic source and drain regions has a profile. A first semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic source region, and conformal with the profile of the metallic source region. A second semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic drain region, and conformal with the profile of the metallic drain region.

Claims (15)

1. A non-planar semiconductor device, comprising:

a semiconducting channel region comprising a three-dimensional body above a substrate, the substrate having a top surface;

a gate electrode stack surrounding at least a top surface and a pair of sidewalls of the three-dimensional body of the semiconductor channel region;

a pair of insulating sidewall spacers adjacent the gate electrode stack;

metallic source and drain regions disposed above the substrate, on either side of the semiconducting channel region, each of the metallic source and drain regions having a profile, wherein a portion of each of the metallic source and drain regions is vertically beneath the gate electrode stack along a direction normal to the top surface of the substrate;

a first semiconducting out-diffusion region disposed in the substrate, between the semiconducting channel region and the metallic source region, and conformal with the profile of the metallic source region, wherein a portion of the first semiconducting out-diffusion region is disposed under one of the pair of insulating sidewall spacers and vertically beneath the gate electrode stack along the direction normal to the top surface of the substrate; and

a second semiconducting out-diffusion region disposed in the substrate, between the semiconducting channel region and the metallic drain region, and conformal with the profile of the metallic drain region, wherein a portion of the second semiconducting out-diffusion region is disposed under another one of the pair of insulating sidewall spacers and vertically beneath the gate electrode stack along the direction normal to the top surface of the substrate, wherein the metallic source and drain regions have rounded profiles, and the first and second semiconducting out-diffusion regions are conformal with the rounded profiles.

2. The non-planar semiconductor device of claim 1 , wherein the metallic source and drain regions comprise a conductive material selected from the group consisting of a metal nitride, a metal carbide, a metal silicide, a metal aluminide, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel or a conductive metal oxide.

3. The non-planar semiconductor device of claim 1 , wherein the metallic source and drain regions uniaxially stress the semiconducting channel region.

4. The non-planar semiconductor device of claim 1 , wherein the semiconductor device is an N-type device, the semiconducting channel region comprises silicon, and the first and second semiconducting out-diffusion regions comprise dopant impurity atoms selected from the group consisting of phosphorous and arsenic.

5. The non-planar semiconductor device of claim 4 , wherein the metallic source and drain regions comprise a material selected from the group consisting of a metal carbide or a metal aluminide.

6. The non-planar semiconductor device of claim 1 , wherein the semiconductor device is a P-type device, the semiconducting channel region comprises silicon, and the first and second semiconducting out-diffusion regions comprise boron dopant impurity atoms.

7. The non-planar semiconductor device of claim 6 , wherein the metallic source and drain regions comprise a material selected from the group consisting of a metal nitride, a metal carbide, or a metal silicide.

8. The non-planar semiconductor device of claim 1 , wherein the substrate is a bulk substrate, and the three-dimensional body is continuous with the bulk substrate.

9. The non-planar semiconductor device of claim 1 , wherein the substrate includes an insulating layer, and the three-dimensional body is an isolated three-dimensional body.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 15, 2022
From: INTEL CORPORATION
To: TAHOE RESEARCH, LTD.
Reel/Frame 061175/0176 →
Continuity (2)
Division 13995419
Related Publication 20170125591A1 · May 4, 2017