3D interconnect structure comprising through-silicon vias combined with fine pitch backside metal redistribution lines fabricated using a dual damascene type approach
View Patent ↗A 3D interconnect structure and method of manufacture are described in which a through-silicon vias (TSVs) and metal redistribution layers (RDLs) are formed using a dual damascene type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and etch stop layer during the process flow.
1. A 3D interconnect structure comprising:
a semiconductor substrate having a front surface and a back surface;
a dual damascene via and redistribution layer (RDL); wherein the via extends through the semiconductor substrate between the front and back surfaces, and the RDL is formed over the back surface in a trench opening; and
an insulating liner layer formed on side surfaces of the dual damascene via and the trench opening, and not formed on bottom surfaces of the dual damascene via and the trench opening.
2. The 3D interconnect structure of claim 1 , further comprising a passivation layer disposed between the back surface and the RDL.
3. The 3D interconnect structure of claim 2 , wherein the passivation layer comprises silicon carbide or silicon nitride.
4. The 3D interconnect structure of claim 1 , wherein the dual damascene via and RDL further comprise a continuous barrier layer formed on the bottom surfaces of the dual damascene via and the trench opening, and on the insulating liner layer formed on the side surfaces of the dual damascene via and the trench opening.
5. The 3D interconnect structure of claim 3 , further comprising:
an array of landing pads arranged over the back surface in a series of rows and columns;
an array of through-silicon vies (TSVs) arranged under the back surface such that the array of TSVs is not directly underneath the array of landing pads; and
a plurality of RDLs running between two of the rows of the landing pads connecting one of the two rows to a corresponding number of TSVs in the array of TSVs.
6. The 3D interconnect structure of claim 5 , wherein the two rows of the landing pads are separated by a pitch of 10 μm to 500 μm.
7. A 3D package comprising:
a base substrate;
a chip stack formed over the base substrate;
wherein the chip stack includes a chip comprising:
a semiconductor substrate having a front surface and a back surface;
a dual damascene via and redistribution layer (RDL); wherein the via extends between the front and back surfaces of the semiconductor substrate, and the RDL is formed over the back surface in a trench opening; and
an insulating liner layer formed on side surfaces of the dual damascene via and the trench opening, and not formed on bottom surfaces of the dual damascene via and the trench opening.
8. The 3D package of claim 7 , wherein the chip is a logic chip.
9. The 3D package of claim 8 , further comprising a system comprising a bus communicatively coupled to the 3D package.
10. The 3D package of claim 8 , wherein the logic chip further comprises:
an array of landing pads arranged over the back surface in a series of rows and columns;
an array of through-silicon vias (TSVs) arranged under the back surface such that the array of TSVs is not directly underneath the array of landing pads; and
a plurality of RDLs running between two of the rows of the landing pads connecting one of the two rows to a corresponding number of TSVs in the array of TSVs.
11. The 3D package of claim 10 , wherein the array of landing pads are coupled with a corresponding array of landing pads of a memory chip.
12. A method of forming a dual damascene 3D interconnect structure comprising:
forming a passivation layer over a back surface of a device wafer, wherein the passivation layer comprises silicon carbide or silicon nitride;
forming a dielectric layer over the passivation layer;
forming a trench opening in the dielectric layer;
forming a via opening in the device wafer between the back surface and a front surface of the device wafer;
forming an insulating liner layer on side surfaces of the via opening and the trench opening but not on bottom surfaces of the via opening and the trench opening;
filling a bulk volume of the via and the trench openinig with a conductive metal to form a via and redistribution layer (RDL) including a landing pad, wherein the via is not directly underneath the landing pad; and
forming a conductive bump over the landing pad.
13. The method of claim 12 , wherein forming the trench opening comprises plasma etching the dielectric layer.
14. The method of claim 13 , wherein the plasma etching comprises using a patterned photoresist layer as a mask, and stopping the plasma etching on the passivation layer.
15. The method of claim 12 , wherein forming the insulating liner layer comprises first depositing an insulating liner material on side and bottom surfaces of the via opening and the trench opening.
16. The method of claim 15 , wherein forming the insulating liner layer further comprises anisotropically etching the insulating liner material from the bottom surfaces of the via opening and the trench opening while retaining a substantial thickness of the insulating liner material on the side surfaces of the via opening and the trench opening.
17. The method of claim 12 , wherein filling the bulk volume of the via opening and the trench opening with a conductive metal comprises electroplating copper.
18. The method of claim 12 , further comprising;
forming an array of landing pads over the back surface in a series of rows and columns;
forming an array of through-silicon vias (TSVs) under the back surface such that the array of TSVs is not directly underneath the array of landing pads; and
forming a plurality of RDLs running between two of the rows of the landing pads connecting one of the two rows to a corresponding number of TSVs in the array of TSVs.
19. The method of claim 18 , wherein the two rows of the landing pads are separated by a pitch of 10 μm to 500 μm.