Digital synthesizable low dropout regulator with adaptive gain
Described is a voltage regulator with adaptive gain, which comprises: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a load, and to receive a second power supply as input; an analog-to-digital converter (ADC) to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative of the first power supply and to generate the digital bus for controlling the plurality of power-gate transistors such that a transfer function of the plurality of power-gate transistors is substantially linear over an operating range.
1. A voltage regulator comprising:
a plurality of power-gate transistors to provide a power supply to a load based on a digital control signal;
an analog-to-digital converter (ADC) to receive the power supply and to generate a digital output representative of the power supply; and
a controller to receive the digital output and to generate the digital control signal based on the digital output representative of the power supply, wherein the controller includes:
a plurality of delay units coupled together in series, wherein a first delay unit of the plurality of delay units receives the digital output representative of the power supply;
a plurality of gain stages to amplify gain of outputs of each of the plurality of delay units to generate respective amplified outputs;
a summer to sum the amplified outputs to generate a summed output; and
a multiplier to multiply the summed output by a factor to modify a gain of a loop formed by the plurality of power-gate transistors, the ADC, and the controller.
2. The voltage regulator of claim 1 , wherein the multiplier is to multiply the summed output by a factor to modify the gain of the loop such that a transfer function of the plurality of power-gate transistors is substantially linear over an operating range.
3. The voltage regulator of claim 1 , wherein the controller comprises:
a sign detector to detect if the summed output is negative or positive, wherein the detected negative or positive summed output is used to determine the factor.
4. The voltage regulator of claim 1 , wherein the plurality of delay units are a first plurality of delay units, wherein the plurality of gain stages are a first plurality of gain stages, and wherein the controller comprises:
a second plurality of delay units coupled together in series, wherein one of the delay units of the second plurality of delay units receives an output of the controller; and
a second plurality of gain stages to amplify gain of outputs of each of the second plurality of delay units.
5. The voltage regulator of claim 1 , further comprising a digital-to-analog converter (DAC) to convert a voltage identification signal (VID) into a plurality of analog signals for the ADC.
6. The voltage regulator of claim 1 , further comprising a decoder to decode an output of the multiplier to generate the digital control signal.
7. The voltage regulator of claim 6 , wherein the decoder is operable to cause the voltage regulator to operate in bypass mode in which all of the plurality of power-gate transistors are turned on.
8. The voltage regulator of claim 6 , wherein the decoder is operable to generate the digital control signal to cause all the plurality of power-gate transistors to turn off.
9. The voltage regulator of claim 1 , wherein the voltage regulator and the load are included in a same integrated circuit die.
10. An apparatus comprising:
a plurality of power-gate transistors to generate a power supply based on a digital control signal;
a controller to receive a digital output representative of the power supply and to generate an output based on a digital signal representative of the power supply, wherein the controller includes:
a plurality of delay units coupled together in series, wherein one of the delay units of the plurality of delay units is to receive the digital signal representative of the power supply;
a plurality of gain stages to amplify gain of outputs of each of the plurality of delay units to generate respective amplified outputs;
a summer to integrate the amplified outputs to generate a summed output; and
a multiplier to multiply the summed output by a factor to generate the output of the controller; and
a decoder to decode the output of the controller to generate the digital control signal.
11. The apparatus of claim 10 , wherein the multiplier is to multiply the summed output by the factor to modify a gain of the apparatus such that a transfer function of the plurality of power-gate transistors is substantially linear over an operating range.
12. The apparatus of claim 10 , wherein the controller comprises:
a sign detector to detect if the summed output is negative or positive, wherein the detected negative or positive summed output is used to determine the factor.
13. The apparatus of claim 10 , wherein the plurality of delay units are a first plurality of delay units, wherein the plurality of gain stages are a first plurality of gain stages, and wherein the controller further comprises:
a second plurality of delay units coupled together in series, wherein one of the delay units of the second plurality of delay units receives the output of the controller; and
a second plurality of gain stages to amplify gain of outputs of each of the second plurality of delay units.
14. The apparatus of claim 10 , wherein the decoder is operable to cause the apparatus to operate in bypass mode in which all of the plurality of power-gate transistors are turned on.
15. The apparatus of claim 10 , wherein the decoder is operable to generate the digital control signal to cause all the plurality of power-gate transistors to turn off.
16. The apparatus of claim 10 , wherein the power supply is to be provided to a load that is on a same integrated circuit die as the plurality of power-gate transistors, the controller, and the decoder.
17. A computing system comprising:
a memory unit;
a processor coupled to the memory unit, the processor having a voltage regulator that includes:
a circuit block;
a plurality of power-gate transistors to provide a power supply to the circuit block based on a digital control signal; and
a controller to receive a digital output and to generate the digital control signal based on a voltage level of the power supply, wherein the controller includes:
a plurality of delay units coupled together in series, wherein a first delay unit of the plurality of delay units receives a digital signal representative of the voltage level of the power supply;
a plurality of gain stages to amplify gain of outputs of each of the plurality of delay units to generate respective amplified outputs;
a summer to sum the amplified outputs to generate a summed output; and
a multiplier to multiply the summed output by a factor to modify a gain of a loop formed by the plurality of power-gate transistors and the controller; and
a wireless interface to enable the processor to communicate with another device through an antenna.
18. The computing system of claim 17 , wherein the multiplier is to multiply the summed output by a factor to modify the gain of the loop such that a transfer function of the plurality of power-gate transistors is substantially linear over an operating range.
19. The computing system of claim 17 , wherein the controller comprises:
a sign detector to detect if the summed output is negative or positive, wherein the detected negative or positive summed output is used to determine the factor.
20. The computing system of claim 17 , wherein the plurality of delay units are a first plurality of delay units, wherein the plurality of gain stages are a first plurality of gain stages, and wherein the controller comprises:
a second plurality of delay units coupled together in series, wherein one of the delay units of the second plurality of delay units is to receive an output of the controller; and
a second plurality of gain stages to amplify gain of outputs of each of the second plurality of delay units.
21. The computing system of claim 17 , further comprising a decoder to decode an output of the multiplier to generate the digital control signal.
22. The computing system of claim 21 , wherein the decoder is operable to cause the apparatus to operate in bypass mode in which all of the plurality of power-gate transistors are turned on; and
wherein the decoder is operable to generate the digital control signal to cause all the plurality of power-gate transistors to turn off.
23. The computing system of claim 17 , further comprising a display unit coupled to the processor.