IP Library › Granted Patent US 10,971,453

Granted Patent B2

US 10,971,453 · App. 16/335,845 · Granted Apr 6, 2021

Semiconductor packaging with high density interconnects

Inventors: Adel A. Elsherbini (Chandler, AZ); Johanna M. Swan (Scottsdale, AZ); Shawna M. Liff (Scottsdale, AZ); Henning Braunisch (Phoenix, AZ); Krishna Bharath (Chandler, AZ); Javier Soto Gonzalez (Chandler, AZ); Javier A. Falcon (Chandler, AZ)

Assignee: Intel Corporation

H01L23/5389 H01L21/4853 H01L21/4857 H01L23/49827 H01L23/49833 H01L23/5383 H01L23/5386 H01L24/00 H01L24/17 H01L24/19 H01L24/20 H01L25/03 H01L25/0657 H01L25/50 H01L25/18 H01L2224/18 H01L2224/214 H01L2225/0651 H01L2225/0652 H01L2225/06513 H01L2225/06517 H01L2225/06562 H01L2225/06582 H01L2225/06589 H01L2924/15153

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Quick Facts

Patent No.: US 10,971,453
App. No.: 16/335,845
Granted: Apr 6, 2021
Kind: B2

External Links

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Abstract

Various embodiments disclosed relate to a semiconductor package. The present semiconductor package includes a substrate. The substrate is formed from alternating conducting layers and dielectric layers. A first active electronic component is disposed on an external surface of the substrate, and a second active electronic component is at least partially embedded within the substrate. A first interconnect region is formed from a plurality of interconnects between the first active electronic component and the second active electronic component. Between the first active electronic component and the substrate a second interconnect region is formed from a plurality of interconnects. Additionally, a third interconnect region is formed from a plurality of interconnects between the second active electronic component and the substrate.

Claims (59)

1. A semiconductor package comprising:

a substrate comprising:

a plurality of conducting layers and dielectric layers;

a first active silicon die disposed on an external surface of the substrate;

a second active silicon die at least partially embedded within the substrate;

a first interconnect region formed from a plurality of interconnects between the first active silicon die and the second active silicon die;

a second interconnect region formed from a plurality of interconnects between the first active silicon die and the substrate; and

a third interconnect region formed from a plurality of interconnects between the second active silicon die and the substrate,

wherein a density of the interconnects of the first interconnect region is greater than a density of the interconnects of at least one of the second interconnect region and the third interconnect region.

2. The semiconductor package of claim 1 , wherein the first interconnect region has a higher density of interconnects than both of the second interconnect region and the third interconnect region.

3. The semiconductor package of claim 1 , wherein the interconnects of the first interconnect region have a pitch ranging from about 20 microns to about 80 microns.

4. The semiconductor package of claim 2 , wherein the interconnects of the second interconnect region have a pitch ranging from about 85 microns to about 350 microns.

5. The semiconductor package of claim 2 , wherein the interconnects of the third interconnect region have a pitch ranging from about 85 microns to about 350 microns.

6. The semiconductor package of claim 2 , wherein a density of the second interconnect region and a density of the third interconnect region are the same.

7. The semiconductor package of claim 1 , wherein the third interconnect region is formed from an interposer comprising:

a top surface;

a bottom surface; and

a fourth interconnect region formed from a plurality of interconnects between the interposer and the substrate;

wherein a first portion of the bottom surface is connected to the interconnects of the third interconnect region; and a second portion of the bottom surface is connected to the interconnects of the fourth interconnect region.

8. A semiconductor package comprising:

a substrate comprising:

a plurality of conducting layers and dielectric layers;

a first active electronic component disposed on an external surface of the substrate;

a second active electronic component at least partially embedded within the substrate;

a first interconnect region formed from a plurality of interconnects between the first active electronic component and the second active electronic component;

a second interconnect region formed from a plurality of interconnects between the first active electronic component and the substrate; and

a third interconnect region formed from a plurality of interconnects between the second active electronic component and the substrate,

9. The semiconductor package of claim 8 , wherein the interconnects of the first interconnect region comprise:

solder balls connected to a bottom surface of the first active electronic component; and

vias connected to a top surface of the second active electronic component,

wherein the solder balls and the vias are connected to each other.

10. The semiconductor package of claim 8 , wherein the interconnects of the second interconnect region comprise:

solder balls connected to a conducting layer of the substrate and the first active electronic component.

11. The semiconductor package of claim 8 , wherein the first active electronic component and the second active electronic component are a first silicon die and a second silicon die.

12. The semiconductor package of claim 8 , and of a central processing unit, a field-programmable gate array, a system on chip, or a graphics processing unit or a combination thereof.

13. The semiconductor package of claim 8 , the second silicon die component is selected from the group consisting of a high-bandwidth memory, a package embedded memory, a flash memory, an embedded nonvolatile memory, a Ill-V die, an accelerator, and a low power double data rate memory.

14. The semiconductor package of claim 8 , wherein the third interconnect region is formed from an interposer comprising:

a top surface;

a bottom surface; and

a fourth interconnect region formed from a plurality of interconnects between the interposer and the substrate,

15. The semiconductor package of claim 14 , wherein the interposer further comprises:

a plurality of thermal vias extending from the bottom surface of the interposer to the top surface of the interposer.

16. The semiconductor package of claim 8 , wherein the third interconnect region is formed from a portion of a conducting layer of the substrate.

17. The semiconductor package of claim 16 , wherein the third interconnect region covers a portion of the second active electronic component.

18. A method of forming a semiconductor package comprising:

placing a first active electronic component on a substrate;

placing a second active electronic component in a recess of the substrate;

forming a first interconnection between the first active electronic component and the second active electronic component;

forming a second interconnection between the first active electronic component and the substrate; and

forming a third interconnection between the second active electronic component and the substrate,

wherein a density of interconnects of the first interconnection is greater than a density of the interconnects of at least one of the second interconnection and the third interconnection.

19. The method of claim 18 , wherein forming the third interconnection comprises:

attaching an interposer to the second active electronic component.

20. The method of claim 19 , wherein attaching the interposer to the second active electronic component comprises:

aligning a set of solder balls of the interposer with the second active electronic component;

heating the set of solder balls; and

cooling the set of solder balk.

Assignments (1)

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 15, 2022

From: INTEL CORPORATION

To: TAHOE RESEARCH, LTD.

Reel/Frame 061175/0176 →