Apparatus to reduce retention failure in complementary resistive memory
View Patent ↗Described is an apparatus which comprises: a complementary resistive memory bit-cell; and a sense amplifier coupled to the complementary resistive memory bit-cell, wherein the sense amplifier includes: a first output node; and a first transistor which is operable to cause a deterministic output on the first output node.
1. An apparatus comprising:
a complementary resistive memory bit-cell; and
a sense amplifier coupled to the complementary resistive memory bit-cell, wherein the sense amplifier includes:
a first output node; and
a first transistor which is operable to cause a deterministic output on the first output node.
2. The apparatus of claim 1 comprises a first keeper device coupled in series to the first transistor.
3. The apparatus of claim 1 comprises a second output node to provide a deterministic complementary output when the first transistor causes deterministic output on the first output node.
4. The apparatus of claim 3 comprises a second transistor coupled to the second output node.
5. The apparatus of claim 4 comprises a second keeper device coupled in series to the second transistor.
6. The apparatus of claim 1 , wherein the first transistor is operable to cause a deterministic output on the first output node when at least one of the resistive memory bit-cells of the complementary resistive memory bit-cell exhibits an uncertain read.
7. The apparatus of claim 1 comprises logic to determine number of ones and zeros in a word to be written to a memory having the complementary resistive memory bit-cell.
8. The apparatus of claim 7 , comprises a polarity bit to store a bit indicating whether the number of ones in the word is greater than a number of zeros in the word.
9. The apparatus of claim 8 comprises logic to invert the word when the polarity bit indicates that the number of ones is greater than the number of zeros in the word.
10. The apparatus of claim 9 , wherein the inverted word is stored in the memory.
11. The apparatus of claim 1 comprises a biasing circuit to bias the first transistor to cause the first transistor to source the deterministic output on the first output node.
12. The apparatus of claim 1 , wherein the complementary resistive memory bit-cell comprises at least one of:
a magnetic tunneling junction (MTJ) device;
a phase change memory (PCM) cell; or
a resistive random access memory (ReRAM) cell.
13. The apparatus of claim 1 , wherein the memory is at least one of:
a magnetic random access memory (MRAM); or
a Phase Change Memory (PCM).
14. An apparatus comprising:
a complementary resistive memory bit-cell;
a bit-line;
a complementary bit-line, wherein the bit-line and the complementary bit-line are coupled to the complementary resistive memory bit-cell;
a word-line coupled to gate terminals of the complementary resistive memory bit-cell; and
a sense amplifier coupled to the complementary resistive memory bit-cell, wherein the sense amplifier is operable to cause a deterministic output regardless of data is stored in the complementary resistive memory bit-cell.
15. The apparatus of claim 14 , wherein the sense amplifier includes:
a first output node; and
a first transistor which is operable to cause the deterministic output on the first output node.
16. The apparatus of claim 15 comprises a first keeper device coupled in series to the first transistor.
17. The apparatus of claim 14 comprises:
a source line; and
a complementary source line, wherein the source line and complementary source line are coupled to the complementary resistive memory bit-cell.
18. A system comprising:
a processor having cache which includes:
an array of complementary resistive memory bit-cells; and
multiplexers coupled to the array; and
at least one sense amplifier coupled to the array, wherein the at least one sense amplifier includes:
a first output node; and
a transistor which is operable to cause a deterministic output on the first output node; and
a wireless interface for allowing the processor to communicate with another device.
19. The system of claim 18 , wherein the processor comprises one or more processor cores, and wherein the array of complementary resistive memory bit-cells is located in a different die than the one or more processor cores in a three dimensional (3D) integrated circuit.
20. The system of claim 18 , wherein the complementary resistive memory bit-cell comprises at least one of:
magnetic tunneling junction (MTJ) device;
a phase change memory (PCM) cell; or
a resistive random access memory (ReRAM) cell.