Inter-die passive interconnects approaching monolithic performance
View Patent ↗Inter-die passive interconnects are lengthened while locating I/O circuitry away from die edge, such that passive interconnect length is agglomerated toward the die edge, and inter-die communication is expedited.
1. A multi-chip package comprising:
a first semiconductive device including a first-die, first input-output circuitry;
a first-die, first on-die routing in contact with the first-die, first input-output circuitry and in contact with a first-die, first electrical contact;
a bridge die in contact with the first-die, first electrical contact;
a bridge-die, first passive routing in contact with the first-die, first electrical contact;
a second semiconductive device in contact with a second-die, first electrical contact that is on the bridge die and in contact with the bridge-die, first passive routing;
a first-die, second on-die routing that contacts a first-die, second electrical contact;
a bridge-die, second passive routing on the bridge die that is in contact with the first-die, second electrical contact;
wherein the bridge-die, second passive routing is coupled to the second die at a second-die contact; and
wherein the bridge-die, second passive routing is in a metallization strata vertically adjacent the bridge-die, first passive routing.
2. The multi-chip package of claim 1 , further including:
a first-die, second input-output circuitry on the first die;
a first-die, second on-die routing in contact with the first-die, second input-output circuitry and in contact with a first-die, second electrical contact;
a bridge-die, second passive routing on the bridge die that is in contact with the first-die, second electrical contact; and
wherein the bridge-die, second passive routing is coupled to the second die at a second-die, second electrical contact.
3. The multi-chip package of claim 1 , further including:
a first-die, second input-output circuitry on the first die;
a first-die, second on-die routing in contact with the first-die, second input-output circuitry and in contact with a first-die, second electrical contact;
a bridge-die, second passive routing on the bridge die that is in contact with the first-die, second electrical contact;
wherein the bridge-die, second passive routing is coupled to the second die at a second-die, second electrical contact; and
a second-die, second on-die routing coupled in a composite passive channel to a second-die, second passive routing.
4. The multi-chip package of claim 1 , further including:
a first-die, second input-output circuitry on the first die;
a first-die, second on-die routing in contact with the first-die, second input-output circuitry and in contact with a first-die, second electrical contact;
a bridge-die, second passive routing on the bridge die that is in contact with the first-die, second electrical contact;
wherein the bridge-die, second passive routing is coupled to the second die at a second-die, second electrical contact;
a second-die, second on-die routing coupled in a composite passive channel to a second-die, second passive routing; and
wherein the second-die, second on-die routing contacts a second-die second input-output circuitry.
5. The multi-chip package of claim 1 , wherein the first die includes a first core-logic region and a second core-logic region, further including:
a first-die, second on-die routing in contact with a first-die, second input-output circuitry that is part of the second core-logic region;
a first-die, second on-die routing in contact with the first-die, second input-output circuitry and in contact with a first-die, second electrical contact, wherein the bridge die is in contact with the first-die, second electrical contact;
a bridge-die, second passive routing in contact with the first-die, second electrical contact;
a second-die, second electrical contact that is on the bridge die and in contact with the bridge-die, second passive routing;
a second-die, second on-die routing in contact with the second-die, second electrical contact; and
a second-die, second input-output circuitry in contact with the second-die, second on-die routing.
6. The multi-chip package of claim 1 , wherein the second die includes a first core-logic region and a second core-logic region, further including:
a first-die, second on-die routing in contact with a first-die, second input-output circuitry;
a first-die, second on-die routing in contact with the first-die, second input-output circuitry and in contact with a first-die, second electrical contact, wherein the bridge die is in contact with the first-die, second electrical contact;
a bridge-die, second passive routing in contact with the first-die, second electrical contact;
a second-die, second electrical contact that is on the bridge die and in contact with the bridge-die, second passive routing;
a second-die, second on-die routing in contact with the second-die, second electrical contact; and
a second-die, second input-output circuitry in contact with the second-die, second on-die routing, and wherein the second-die, second input-output circuitry is part of the second core-logic region.
7. The multi-chip package of claim 1 , further including:
a third die coupled to the bridge die by a passive signal channel, wherein the third die contacts a first-die third contact on the first die.
8. The multi-chip package of claim 1 , further including:
a first-die, second on-die routing that contacts a first-die, second electrical contact;
a bridge-die, second passive routing on the bridge die that is in contact with the first-die, second electrical contact; and
wherein the bridge-die, second passive routing is coupled to the second die at a bridge-die contact.
9. The multi-chip package of claim 1 , further including:
a first-die, second on-die routing that contacts a first-die, second electrical contact;
a bridge-die, second passive routing on the bridge die that is in contact with the first-die, second electrical contact;
wherein the bridge-die, second passive routing is coupled to the second die at a second-die contact; and
wherein the bridge-die, second passive routing is in a metallization strata vertically adjacent the bridge-die, first passive routing, and wherein the metallization strata includes at least two different cross-section sizes, including a first small size and a second medium size.
10. The multi-chip package of claim 1 , further including:
a first-die, second on-die routing that contacts a first-die, second electrical contact;
a bridge-die, second passive routing on the bridge die that is in contact with the first-die, second electrical contact;
wherein the bridge-die, second passive routing is coupled to the second die at a second-die contact; and
wherein the bridge-die, second passive routing is in a metallization strata vertically adjacent the bridge-die, first passive routing, and wherein the metallization strata includes at least two different cross-section sizes, including a first small size, a second medium size, and a third giant size.
11. The multi-chip package of claim 1 , further including:
a first-die, second on-die routing that contacts a first-die, second electrical contact;
a bridge-die, second passive routing on the bridge die that is in contact with the first-die, second electrical contact;
wherein the bridge-die, second passive routing is coupled to the second die at a second-die contact;
wherein the bridge-die, second passive routing is in a metallization strata vertically adjacent the bridge-die, first passive routing; and
an adjacent first die adjacent the first die, wherein a converged mesh-stop (CMS) region in the adjacent first die is coupled to the first-die, first on-die routing.
12. The multi-chip package of claim 1 , further including:
a first-die, second on-die routing that contacts a first-die, second electrical contact;
a bridge-die, second passive routing on the bridge die that is in contact with the first-die, second electrical contact;
wherein the bridge-die, second passive routing is coupled to the second die at a second-die contact;
wherein the bridge-die, second passive routing is in a metallization strata vertically adjacent the bridge-die, first passive routing;
an adjacent first die adjacent the first die, wherein a converged mesh-stop (CMS) region in the adjacent first die is coupled to the first-die, first on-die routing; and
an adjacent second die adjacent the second die, wherein a converged mesh-stop (CMS) region in the adjacent second die is coupled to the second-die, first on-die routing.
13. The multi-chip package of claim 1 , further including:
a first-die, second on-die routing that contacts a first-die, second electrical contact;
a bridge-die, second passive routing on the bridge die that is in contact with the first-die, second electrical contact;
wherein the bridge-die, second passive routing is coupled to the second die at a second-die contact;
wherein the bridge-die, second passive routing is in a metallization strata vertically adjacent the bridge-die, first passive routing; and
an adjacent second die adjacent the second die, wherein a converged mesh-stop (CMS) region in the adjacent second die is coupled to the second-die, first on-die routing.
14. The multi-chip package of claim 1 , further including:
a first-die, second on-die routing that contacts a first-die, second electrical contact;
a bridge-die, second passive routing on the bridge die that is in contact with the first-die, second electrical contact;
wherein the bridge-die, second passive routing is coupled to the second die at a second-die contact; and
wherein the bridge-die, second passive routing is in a metallization strata and laterally adjacent the bridge-die, first passive routing.
15. The multi-chip package of claim 1 , further including:
a first-die, second on-die routing that contacts a first-die, second electrical contact;
a bridge-die, second passive routing on the bridge die that is in contact with the first-die, second electrical contact;
wherein the bridge-die, second passive routing is coupled to the second die at a second-die contact;
wherein the bridge-die, second passive routing is in a metallization strata and laterally adjacent the bridge-die, first passive routing; and
an adjacent first die adjacent the first die, wherein a converged mesh-stop (CMS) region in the adjacent first die is coupled to the first-die, first on-die routing.
16. The multi-chip package of claim 1 , further including:
a first-die, second on-die routing that contacts a first-die, second electrical contact;
a bridge-die, second passive routing on the bridge die that is in contact with the first-die, second electrical contact;
wherein the bridge-die, second passive routing is coupled to the second die at a second-die contact;
wherein the bridge-die, second passive routing is in a metallization strata and laterally adjacent the bridge-die, first passive routing; and
an adjacent second die adjacent the second die, wherein a converged mesh-stop (CMS) region in the adjacent second die is coupled to the second-die, first on-die routing.
17. The multi-chip package of claim 1 , further including:
a first-die, second on-die routing that contacts a first-die, second electrical contact;
a bridge-die, second passive routing on the bridge die that is in contact with the first-die, second electrical contact;
wherein the bridge-die, second passive routing is coupled to the second die at a second-die contact;
wherein the bridge-die, second passive routing is in a metallization strata and laterally adjacent the bridge-die, first passive routing;
an adjacent first die adjacent the first die, wherein a converged mesh-stop (CMS) region in the adjacent first die is coupled to the first-die, first on-die routing; and
an adjacent second die adjacent the second die, wherein a converged mesh-stop (CMS) region in the adjacent second die is coupled to the second-die, first on-die routing.
18. A multi-chip package comprising:
a first die with signal routing, including:
a converged mesh-stop (CMS) region adjacent a core logic region;
first on-die input-output (I/O) circuitry adjacent the CMS region and spaced apart from a modular die-fabric interconnect (MDFI);
first-die, first on-die passive routing between the first on-die I/O circuitry and a first electrical contact that contacts a bride die, wherein the first electrical contact is closest to a first edge of the bridge die;
bridge-die passive routing on the bridge die between the first electrical contact and a second electrical contact on the bridge die, wherein the second electrical contact is closest to a second edge of the bridge die; and
a second die that contacts the second electrical contact.
19. The multi-chip package of claim 18 , wherein the second die includes a second-die, first on-die passive routing between the second electrical contact and a second-die, first on-die I/O circuitry.
20. The multi-chip package of claim 18 , wherein the second die includes a second-die, first on-die passive routing between the second electrical contact and a second-die, first on-die I/O circuitry, further including:
a third die contacting the bridge die, wherein the third die is coupled to the first die by a composite passive signal channel.
21. The multi-chip package of claim 18 , wherein the second die includes a second-die, first on-die passive routing between the second electrical contact and a second-die, first on-die I/O circuitry, further including:
a first adjacent die adjacent the first die, wherein the first adjacent die includes a passive signal channel that contacts the first die; and
a second adjacent die adjacent the second die, wherein the second adjacent die includes a passive signal channel that contacts the second die.