Plural matrices of execution units for processing matrices of row dependent instructions in single clock cycle in super or separate mode
View Patent ↗A matrix of execution blocks form a set of rows and columns. The rows support parallel execution of instructions and the columns support execution of dependent instructions. The matrix of execution blocks process a single block of instructions specifying parallel and dependent instructions.
1. An apparatus, comprising:
a memory storing a matrix of instructions;
a pipeline comprising a decoder to decode the matrix of instructions and a matrix of execution units to execute the matrix of instructions, the matrix of instructions includes a set of instruction rows and instruction columns, each instruction within the same row across all columns is executed in parallel by a corresponding sub-set of execution units of the matrix of execution units and instructions dependent upon source instructions of an instruction row are in a subsequent instruction row of the matrix of instructions;
a first sub-set of execution units corresponding to a row of the instruction matrix computes and forwards first data results to a second sub-set of execution units of a subsequent row of the matrix of execution units in a single clock cycle and without pipeline buffering;
the second sub-set of execution units separately receives, from the matrix of instructions, instructions dependent upon the first data results;
the second sub-set of execution units in the same single clock cycle, and without pipeline buffering, computes and forwards second data results to a third sub-set of execution units of a subsequent row of the matrix of execution units; and
the third sub-set of execution units separately receives, from the matrix of instructions, instructions dependent upon the second data results;
wherein the matrix of instructions is one of a plurality of matrices of instructions;
wherein the matrix of execution units is one of a plurality of matrices of execution units; and
wherein the plurality of matrices of execution units is alternately operative to:
execute combined instruction matrices forming a super instruction matrix;
independently execute instruction matrices in a threaded mode where separate threads execute simultaneously on execution units; and
simultaneously execute different, non-dependent instruction matrices.
2. The apparatus of claim 1 wherein the matrix of execution units produces slices of digital output at different rates.
3. The apparatus of claim 2 wherein different digits have different bit widths.
4. The apparatus of claim 1 wherein the matrix of execution units includes modified Booth encoding.
5. The apparatus of claim 4 wherein the modified Booth encoding inserts zeros at digit slice boundaries.
6. The apparatus of claim 1 wherein the matrix of execution units includes a right shifter with first sliced digits applied to a first stack of multiplexers and second sliced digits applied to a second stack of multiplexers, wherein the first stack of multiplexers is larger than the second stack of multiplexers.
7. The apparatus of claim 1 wherein the matrix of execution units includes a left shifter with first sliced digits applied to a first stack of multiplexers and second sliced digits applied to a second stack of multiplexers, wherein the second stack of multiplexers is larger than the first stack of multiplexers.
8. The apparatus of claim 1 further comprising a memory with a time lag configuration to produce a first slice of data followed by a time lagged second slice of data.
9. The apparatus of claim 1 further comprising a floating point multiply accumulate unit configured to implement multiplication, addition, right shift, left shift, and shuffle operations.
10. The apparatus of claim 1 wherein each matrix of instructions has a matrix number to enforce dependency maintenance between the matrices of instructions.
11. The apparatus of claim 1 wherein the matrix of instructions includes Single Instruction Multiple Data (SIMD) instructions.
12. The apparatus of claim 1 wherein the matrix of instructions includes a Multiple Instructions Multiple Data (MIMD) instructions.
13. The apparatus of claim 1 wherein the matrix of instructions includes a combination of Single Instruction Multiple Data (SIMD) instructions and Multiple Instructions Multiple Data (MIMD) instructions.
14. The apparatus of claim 1 wherein the matrix of instructions is formed by a run time system.
15. The apparatus of claim 1 wherein the matrix of instructions is formed by hardware.
16. The apparatus of claim 1 wherein the matrix of instructions is formed by a compiler.