Method and apparatus for sorting elements in hardware structures

1. A method for sorting elements in hardware structures, said method comprising:

selecting a plurality of elements to order from an unordered input queue (UIQ) within a range in response to finding a match between at least one most significant bit of said range and corresponding bits of a respective identifier operable to tag each of said plurality of elements, wherein said UIQ comprises a plurality of out of order elements;

presenting each of said plurality of elements to a respective multiplexer; and

generating a select signal for an enabled multiplexer corresponding to each element in said plurality of elements in response to finding a match between at least one least significant bit of a respective identifier operable to tag each of said plurality of elements and a port number of an ordered retirement queue.

2. The method of claim 1 , further comprising:

forwarding a packet corresponding to a selected element identifier to a matching port number of said ordered queue from said enabled multiplexer.

3. The method of claim 2 , further comprising:

generating a write enable for said matching port number by performing a logical OR operation of said select signal; and

writing said packet into said matching port number of said ordered queue.

4. The method of claim 2 , wherein said UIQ is disposed in a module of a pipeline for an out of order microprocessor, wherein said module is selected from a group consisting of: a register file and a load-store queue.

5. The method of claim 4 , wherein said selecting and said generating are performed in response to a communication protocol controlled by a reorder buffer in said pipeline.

6. The method of claim 5 , wherein said communication protocol communicates said range and a number of elements to be ordered to said module.

7. The method of claim 6 , wherein said ordered queue comprises elements to be retired from said module in a retirement cycle of said pipeline.

8. The method of claim 5 , wherein a respective identifier for each of said plurality of elements corresponds to a location in said reorder buffer wherein said plurality of elements are stored prior to being entered into said UIQ.

9. The method of claim 4 , wherein said plurality of elements are entered into said UIQ of said register file from a write back module of said pipeline.

10. The method of claim 4 , wherein said plurality of elements are entered into said UIQ of said register file from a reorder buffer in said pipeline.

11. A processor unit configured to perform a method for sorting elements in hardware structures, said method comprising:

selecting a plurality of elements to order from an unordered input queue (UIQ) within a range in response to finding a match between at least one most significant bit of said range and corresponding bits of a respective identifier operable to tag each of said plurality of elements, wherein said UIQ comprises a plurality of out of order elements;

presenting each of said plurality of elements to a respective multiplexer; and

generating a select signal for an enabled multiplexer corresponding to each element in said plurality of elements in response to finding a match between at least one least significant bit of a respective identifier operable to tag each of said plurality of elements and a port number of an ordered retirement queue.

12. The process unit as described in claim 11 , wherein said method further comprises:

forwarding a packet corresponding to a selected element identifier to a matching port number of said ordered queue from said enabled multiplexer.

13. The processor unit as described in claim 12 , wherein said method further comprises:

generating a write enable for said matching port number by performing a logical OR operation of said select signal; and

writing said packet into said matching port number of said ordered queue.

14. The processor unit as described in claim 12 , wherein said processor unit is an out of order microprocessor and wherein said UIQ is maintained in a module of a pipeline for said out of order microprocessor, wherein said module is selected from a group consisting of: a register file and a load-store queue.

15. The processor unit as described in claim 14 , wherein said selecting and said generating are performed in response to a communication protocol controlled by a reorder buffer in said pipeline.

16. The processor unit as described in claim 15 , wherein said communication protocol communicates said range and a number of elements to be ordered to said module.

17. The processor unit as described in claim 16 , wherein said ordered queue comprises elements to be retired from said module in a retirement cycle of said pipeline.

18. The processor unit as described in claim 15 , wherein a respective identifier for each of said plurality of elements corresponds to a location in said reorder buffer wherein said plurality of elements are stored prior to being entered into said UIQ.

19. The processor unit as described in claim 14 , wherein said plurality of elements are entered into said UIQ of said register file from a write back module of said pipeline.

20. The processor unit as described in claim 14 , wherein said plurality of elements are entered into said UIQ of said register file from a reorder buffer in said pipeline.

21. An apparatus for sorting elements in hardware structures, said apparatus comprising:

a memory;

a processor communicatively coupled to said memory, wherein said processor is configured to process instructions out of order, and further wherein said processor is configured to:

select a plurality of elements to order from an unordered input queue (UIQ) within a range in response to finding a match between at least one most significant bit of said range and corresponding bits of a respective identifier operable to tag each of said plurality of elements, wherein said UIQ comprises a plurality of out of order elements;

present each of said plurality of elements to a respective multiplexer; and

generate a select signal for an enabled multiplexer corresponding to each element in said plurality of elements in response to finding a match between at least one least significant bit of a respective identifier operable to tag each of said plurality of elements and a port number of an ordered retirement queue.

22. The apparatus of claim 21 , wherein the processor is further configured to:

forward a packet corresponding to a selected element identifier to a matching port number of said ordered queue from said enabled multiplexer.

23. The apparatus of claim 22 , wherein said processor is further configured to:

generate a write enable for said matching port number by performing a logical OR operation of said select signal; and

write said packet into said matching port number of said ordered queue.

24. The apparatus of claim 22 , wherein said plurality of elements correspond with said instructions processed out of order by said processor.