Instruction sequence buffer to store branches having reliably predictable instruction sequences
View Patent ↗A method for outputting reliably predictable instruction sequences. The method includes tracking repetitive hits to determine a set of frequently hit instruction sequences for a microprocessor, and out of that set, identifying a branch instruction having a series of subsequent frequently executed branch instructions that form a reliably predictable instruction sequence. The reliably predictable instruction sequence is stored into a buffer. On a subsequent hit to the branch instruction, the reliably predictable instruction sequence is output from the buffer.
1. A method for outputting predictable instruction sequences, comprising
tracking repetitive hits to determine a set of frequently hit instruction sequences for a microprocessor, wherein the tracking comprises monitoring execution of branches and predicting an outcome of the branches to assemble the set of frequently hit instruction sequences;
out of the set, identifying a branch instruction having a series of subsequent frequently executed branch instructions that form a predictable instruction sequence,
storing the predictable instruction sequence into a buffer; and
on a subsequent hit to the branch instruction, outputting the predictable instruction sequence from the buffer.
2. The method of claim 1 , wherein the buffer storing the predictable instruction sequence is indexed in at least two ways.
3. The method of claim 1 , wherein an address of a branch instruction is used to index the buffer.
4. The method of claim 3 , wherein addresses of a plurality of following branches are used as tags to index the buffer.
5. The method of claim 3 , wherein a plurality of branch prediction bits are used as tags to index the buffer.
6. The method of claim 3 , wherein a hash of the address of the branch instruction is used to index the buffer.
7. The method of claim 1 , wherein compare logic is used to evaluate the predictable instruction sequence to determine whether the sequence should be evicted from the buffer.
8. A system for outputting predictable instruction sequences, said system comprising:
a fetch module that accesses a plurality of instructions that comprise multiple branch instructions;
a buffer that stores predictable instruction sequences;
a sequence predictor operable to monitor execution of branches and predict an outcome of the branches in order to assemble a set of frequently hit instruction sequences for a microprocessor from the plurality of instructions;
wherein the sequence predictor is operable to track repetitive hits to determine the set of frequently hit instruction sequences;
out of the set, the sequence predictor is further operable to identify a branch instruction having a series of subsequent frequently executed branch instructions that form a predictable instruction sequence,
wherein the fetch module is operable to store the predictable instruction sequence into the buffer; and
on a subsequent hit to the branch instruction, the fetch module is operable to access the predictable instruction sequence from the buffer.
9. The system of claim 8 , wherein the buffer storing the predictable instruction sequence is indexed in at least two ways.
10. The system of claim 8 , wherein an address of a branch instruction is used to index the buffer.
11. The system of claim 10 , wherein addresses of a plurality of following branches are used as tags to index the buffer.
12. The system of claim 10 , wherein a plurality of branch prediction bits are used as tags to index the buffer.
13. The system of claim 10 , wherein a hash of the address of the branch instruction is used to index the buffer.
14. The system of claim 8 , further comprising compare logic operable to evaluate the predictable instruction sequence to determine whether the sequence should be evicted from the buffer.
15. A microprocessor that implements a method of identifying instructions, said microprocessor comprising:
a microprocessor pipeline;
a fetch module comprised in the microprocessor pipeline wherein the fetch module accesses a plurality of instructions that comprise multiple branch instructions;
a sequence predictor operable to monitor execution of branches and predict an outcome of the branches to assemble a set of frequently hit instruction sequences from the plurality of instructions; and
a buffer coupled to the fetch module:
wherein the sequence predictor is operable to track repetitive hits to determine the set of frequently hit instruction sequences;
out of the set, the sequence predictor is operable to identify a branch instruction having a series of subsequent frequently executed branch instructions that form a predictable instruction sequence,
wherein the fetch module is operable to store the predictable instruction sequence into the buffer; and
on a subsequent hit to the branch instruction, the fetch module is operable to access the predictable instruction sequence from the buffer.
16. The microprocessor of claim 15 , wherein the buffer storing the predictable instruction sequence is indexed in at least two ways.
17. The microprocessor of claim 15 , wherein an address of a branch instruction is used to index the buffer.
18. The microprocessor of claim 17 , wherein addresses of a plurality of following branches are used as tags to index the buffer.
19. The microprocessor of claim 17 , wherein a plurality of branch prediction bits are used as tags to index the buffer.
20. The microprocessor of claim 17 , wherein a hash of the address of the branch instruction is used to index the buffer.
21. The method of claim 1 , wherein the branch instruction identified is a frequently hit and predicted branch instruction.