IP Library Granted Patent US 9,569,216
Granted Patent B2
US 9,569,216 · App. 14/213,115 · Granted Feb 14, 2017

Method for populating a source view data structure by using register template snapshots

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Quick Facts
Patent No.
US 9,569,216
App. No.
14/213,115
Granted
Feb 14, 2017
Kind
B2
Abstract

A method for populating a source view data structure by using register template snapshots. The method includes receiving an incoming instruction sequence using a global front end; grouping the instructions to form instruction blocks; using a plurality of register templates to track instruction destinations and instruction sources by populating the register template with block numbers corresponding to the instruction blocks, wherein the block numbers corresponding to the instruction blocks indicate interdependencies among the blocks of instructions; populating a source view data structure, wherein the source view data structure stores sources corresponding to the instruction blocks as recorded by the plurality of register templates; and determining which of the plurality of instruction blocks are ready for dispatch by using the populated source view data structure.

Claims (36)

1. A method of populating a source view data structure by using a register template, the method comprising:

receiving an incoming instruction sequence using a global front end;

grouping the instructions to form instruction blocks;

tracking instruction destinations by populating the register template with block numbers corresponding to the instruction blocks, wherein the block numbers corresponding to the instruction blocks indicate interdependencies among the instruction blocks, wherein the tracking comprises an incoming instruction block writing its respective block number into fields of the register template corresponding to destination registers referred to by the incoming instruction block, and wherein further the register template is updated by an arrival of the incoming instruction block;

the incoming instruction block reading fields of the register template corresponding to its register sources to retrieve its instruction sources;

populating a source view data structure, wherein the source view data structure stores the instruction sources corresponding to the instruction blocks as read from the register template by the incoming instruction block, wherein each incoming instruction block updates the source view data structure with instruction source information; and

determining which of the plurality of instruction blocks are ready for dispatch by using the populated source view data structure.

2. The method of claim 1 , wherein the source view data structure is part of a scheduler architecture.

3. The method of claim 1 , wherein information about instructions referred to by the blocks is stored in the instruction view data structure.

4. The method of claim 1 , wherein information about registers referred to by the blocks is stored in the register view data structure.

5. The method of claim 1 , wherein the register template comprises data structures storing dependency and inheritance information referred to by the blocks.

6. The method of claim 1 , wherein the source view data structure determines when a particular block can be dispatched, wherein the determining comprises checking if a ready bit corresponding to each instruction source of the particular block is set.

7. A non-transitory computer readable memory having computer readable code which when executed by a computer system causes the computer system to implement a method for populating a source view data structure by using a register template, comprising:

receiving an incoming instruction sequence using a global front end;

grouping the instructions to form instruction blocks;

tracking instruction destinations by populating the register template with block numbers corresponding to the instruction blocks, wherein the block numbers corresponding to the instruction blocks indicate interdependencies among the instruction blocks, wherein the tracking comprises an incoming instruction block writing its respective block number into fields of the register template corresponding to destination registers referred to by the incoming instruction block, and wherein further the register template is updated by an arrival of the incoming instruction block;

the incoming instruction block reading fields of the register template corresponding to its register sources to retrieve its instruction sources;

populating a source view data structure, wherein the source view data structure stores the instruction sources corresponding to the instruction blocks as read from the register template by the incoming instruction block, wherein each incoming instruction block updates the source view data structure with instruction source information; and

determining which of the plurality of instruction blocks are ready for dispatch by using the populated source view data structure.

8. The computer readable media of claim 7 , wherein the source view data structure is part of a scheduler architecture.

9. The computer readable media of claim 7 , wherein information about instructions referred to by the blocks is stored in the instruction view data structure.

10. The computer readable media of claim 7 , wherein information about registers referred to by the blocks is stored in the register view data structure.

11. The computer readable media of claim 7 , wherein the register template comprises data structures storing dependency and inheritance information referred to by the blocks.

12. The computer readable media of claim 7 , wherein the source view data structure determines when a particular block can be dispatched, wherein the determining comprises checking if a ready bit corresponding to each instruction source of the particular block is set.

13. A computer system having a processor coupled to a memory, wherein the memory has computer readable instructions which when executed by the computer system cause the computer system to implement a method for populating a source view data structure by using a register template, comprising:

receiving an incoming instruction sequence using a global front end;

grouping the instructions to form instruction blocks;

tracking instruction destinations by populating the register template with block numbers corresponding to the instruction blocks, wherein the block numbers corresponding to the instruction blocks indicate interdependencies among the instruction blocks, wherein the tracking comprises an incoming instruction block writing its respective block number into fields of the register template corresponding to destination registers referred to by the incoming instruction block, and wherein further the register template is updated by an arrival of the incoming instruction block;

the incoming instruction block reading fields of the register template corresponding to its register sources to retrieve its instruction sources;

populating a source view data structure, wherein the source view data structure stores the instruction sources corresponding to the instruction blocks as read from the register template by the incoming instruction block, wherein each incoming instruction block updates the source view data structure with instruction source information; and

determining which of the plurality of instruction blocks are ready for dispatch by using the populated source view data structure.

14. The computer system of claim 13 , wherein the source view data structure is part of a scheduler architecture.

15. The computer system of claim 13 , wherein information about instructions referred to by the blocks is stored in the instruction view data structure.

16. The computer system of claim 13 , wherein information about registers referred to by the blocks is stored in the register view data structure.

17. The computer system of claim 13 , wherein the register template comprises data structures storing dependency and inheritance information referred to by the blocks.

18. The computer system of claim 13 , wherein the source view data structure determines when a particular block can be dispatched, wherein the determining comprises checking if a ready bit corresponding to each instruction source of the particular block is set.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 14, 2016
From: SOFT MACHINES, INC.
To: INTEL CORPORATION
Reel/Frame 040631/0915 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 18, 2014
From: ABDALLAH, MOHAMMAD
To: SOFT MACHINES, INC.
Reel/Frame 032465/0449 →