Method for implementing a reduced size register view data structure in a microprocessor
View Patent ↗A method for implementing a reduced size register view data structure in a microprocessor. The method includes receiving an incoming instruction sequence using a global front end; grouping the instructions to form instruction blocks; using a plurality of multiplexers to access ports of a scheduling array to store the instruction blocks as a series of chunks.
1. A method of implementing a reduced size register view data structure in a microprocessor, comprising:
receiving an incoming instruction sequence using a global front end;
grouping instructions of the incoming instruction sequence to form instruction blocks;
performing chunking by using a plurality of multiplexers to access ports of a scheduling array comprising entries to store the instruction blocks as a series of chunks, wherein the scheduling array comprises one write port per entry, and is accessed by using a multiplexing structure before allocating to the scheduling array,
wherein each multiplexer in the plurality of multiplexers is coupled to multiple entries in the scheduling array via a corresponding write port of each entry.
2. The method of claim 1 , wherein the chunking reduces a number of write ports into each entry of the scheduling array from 4 to 1 by using four multiplexers of said plurality of multiplexers.
3. The method of claim 1 , wherein chunking reduces a number of write ports into each entry of the scheduling array from 4 to 1 by using four multiplexers of said plurality of multiplexers while still packing entries in the scheduler array without leaving any unoccupied entries.
4. The method of claim 1 , wherein chunks of the series of chunks sent to the scheduling array are stored temporarily in a separate intermediate allocation buffer.
5. The method of claim 1 , wherein chunks of the series of chunks sent to the scheduling array are stored temporarily in a separate intermediate allocation buffer prior to be received by write ports of the entries.
6. A non-transitory computer readable media having computer readable code which when executed by a computer system causes the computer system to implement a method of implementing a reduced size register view data structure in a microprocessor, the method comprising:
receiving an incoming instruction sequence using a global front end;
grouping instructions of the incoming instruction sequence to form instruction blocks;
performing chunking by using a plurality of multiplexers to access ports of a scheduling array comprising entries to store the instruction blocks as a series of chunks, wherein the scheduling array comprises one write port per entry, and is accessed by using a multiplexing structure before allocating to the scheduling array,
wherein each multiplexer in the plurality of multiplexers is coupled to multiple entries in the scheduling array via a corresponding write port of each entry.
7. The computer readable media of claim 6 , wherein the chunking reduces a number of write ports into each entry of the scheduling array from 4 to 1 by using four multiplexers of said plurality of multiplexers.
8. The computer readable media of claim 6 , wherein chunking reduces a number of write ports into each entry of the scheduling array from 4 to 1 by using four multiplexers of said plurality of multiplexers while still packing entries in the scheduler array without leaving any unoccupied entries.
9. The computer readable media of claim 6 , wherein chunks of the series of chunks sent to the scheduling array are stored temporarily in a separate intermediate allocation buffer.
10. A computer system having a processor coupled to a memory having computer readable code, which when executed by the computer system cause the computer system to implement operations for implementing a reduced size register view data structure in a microprocessor, comprising:
receiving an incoming instruction sequence using a global front end;
grouping instructions of the incoming instruction sequence to form instruction blocks;
performing chunking by using a plurality of multiplexers to access ports of a scheduling array comprising entries to store the instruction blocks as a series of chunks, wherein the scheduling array comprises one write port per entry, and is accessed by using a multiplexing structure before allocating to the scheduling array,
wherein each multiplexer in the plurality of multiplexers is coupled to multiple entries in the scheduling array via a corresponding write port of each entry.
11. The computer system of claim 10 , wherein the chunking reduces a number of write ports into each entry of the scheduling array from 4 to 1 by using four multiplexers of said plurality of multiplexers.
12. The computer system of claim 10 , wherein chunking reduces a number of write ports into each entry of the scheduling array from 4 to 1 by using four multiplexers of said plurality of multiplexers while still packing entries in the scheduler array without leaving any unoccupied entries.
13. The computer system of claim 10 , wherein chunks of the series of chunks sent to the scheduling array are stored temporarily in a separate intermediate allocation buffer.
14. The computer system of claim 13 , wherein chunks stored temporarily in the intermediate allocation buffer are transferred to the scheduling array when the scheduling array has free space.
15. The computer system of claim 13 , wherein allocation of entries into the scheduling array starts with an instruction block in a top most position within the incoming instruction blocks.