Multilevel conversion table cache for translating guest instructions to native instructions
View Patent ↗A method for translating instructions for a processor. The method includes accessing a guest instruction and performing a first level translation of the guest instruction using a first level conversion table. The method further includes outputting a resulting native instruction when the first level translation proceeds to completion. A second level translation of the guest instruction is performed using a second level conversion table when the first level translation does not proceed to completion, wherein the second level translation further processes the guest instruction based upon a partial translation from the first level conversion table. The resulting native instruction is output when the second level translation proceeds to completion.
1. A method for translating instructions for a processor, comprising:
accessing a guest instruction;
performing a first level translation of the guest instruction by comparing the guest instruction to a plurality of group masks and a plurality of tags in a first level conversion table, wherein the comparing is to identify a type of guest instruction;
responsive to a hit for the comparing, outputting a corresponding mapping of a pattern from a mappings table corresponding to the first level conversion table; and
performing a second level translation of the guest instruction by comparing the guest instruction to a plurality of group masks and a plurality of tags in a second level conversion table, wherein the comparing is to output a resulting native instruction in response to the second level translation completion.
2. The method of claim 1 , wherein the performing the first level translation and the performing the second level translation further comprises:
serially detecting bit fields in the guest instruction; and
substituting corresponding bit fields in an equivalent native instruction as the bit fields are detected.
3. The method of claim 2 , wherein the first level conversion table and the second level conversion table include a control field operable to identify a next relevant bit field to be substituted in the equivalent native instruction.
4. The method of claim 1 , wherein the plurality of tags in the first level conversion table and the plurality of tags in the second level conversion table determine pattern matches and the plurality of group masks in the first level conversion table and the plurality of group masks in the second level conversion table hide non-relevant bits of patterns.
5. The method of claim 4 , wherein the plurality of group masks in the first level conversion table and the plurality of group masks in the second level conversion table hide non-relevant bits of an input pattern to facilitate match detection.
6. The method of claim 1 , wherein the first level conversion table and the second level conversion table each store group mask and tag pairs in a prioritized manner.
7. The method of claim 6 , wherein the performing the first level translation and the performing the second level translation further comprises:
reading the group mask and tag pairs in the first level conversion table and the second level conversion table in order of priority to perform the comparing.
8. The method of claim 7 , further comprising:
logging the guest instruction to the resulting native instruction mapping in a conversion lookaside buffer.
9. The method of claim 1 , further comprising:
transmitting the resulting native instruction to a native conversion buffer.
10. A system having executable instructions stored in a non-transitory computer-readable medium for translating instructions for a processor, comprising:
a guest fetch buffer to access a guest instruction;
a first level conversion table to perform a first level translation of the guest instruction by comparing the guest instruction to a plurality of group masks and a plurality of tags in the first level conversion table, wherein the comparing is to identify a group to which the guest instruction belongs;
a mapping table to output a corresponding mapping of a pattern in response to a hit for the comparing in the corresponding first level conversion table;
a second level conversion table to perform a second level translation of the guest instruction by comparing the guest instruction to a plurality of group masks and a plurality of tags in the second level conversion table, wherein the comparing is to output a resulting native instruction in response to the second level translation completion.
11. The system of claim 10 , wherein the first level conversion table and the second level conversion table include substitute fields for substituting native instructions for guest instructions and control fields for controlling the first level conversion table and the second level conversion table.
12. The system of claim 10 , wherein the first level conversion table and the second level conversion table are further to:
serially detect bit fields in the guest instruction; and
substitute corresponding bit fields in an equivalent native instruction as the bit fields are detected.
13. The system of claim 12 , wherein the first level conversion table and the second level conversion table include a control field operable to identify a next relevant bit field to be substituted in the equivalent native instruction.
14. The system of claim 10 , wherein the plurality of tags in the first level conversion table and the plurality of tags in the second level conversion table determine pattern matches and the plurality of group masks in the first level conversion table and the plurality of group masks in the second level conversion table hide non-relevant bits of patterns.
15. The system of claim 14 , wherein the plurality of group masks in the first level conversion table and the plurality of group masks in the second level conversion table hide non-relevant bits of an input pattern to facilitate match detection.
16. The system of claim 10 , wherein the first level conversion table and the second level conversion table each store group mask and tag pairs in a prioritized manner.
17. The system of claim 16 , wherein the first level conversion table and the second level conversion table are further to:
read the group mask and tag pairs in the first level conversion table and the second level conversion table in order of priority to perform the comparing.
18. The system of claim 10 , further comprising:
a conversion lookaside buffer to log a mapping of the guest instruction to the resulting native instruction.
19. A microprocessor that implements a method of translating instructions, said microprocessor comprises:
a microprocessor pipeline;
a hardware accelerator module coupled to the microprocessor pipeline, wherein the hardware accelerator module further comprises:
a plurality of conversion tables for translating guest instructions into corresponding native instructions, wherein the conversion tables function by:
accessing a guest instruction;
performing a first level translation of the guest instruction by comparing the guest instruction to a plurality of group masks and a plurality of tags in a first level conversion table, wherein the comparing is to identify a type of guest instruction;
responsive to a hit for the comparing, outputting a corresponding mapping of a pattern from a mappings table corresponding to the first level conversion table; and
performing a second level translation of the guest instruction by comparing the guest instruction to a plurality of group masks and a plurality of tags in a second level conversion table, wherein the comparing is to output a resulting native instruction in response to the second level translation completion.
20. The microprocessor of claim 19 , wherein the first level conversion table and the second level conversion table are further to:
serially detect bit fields in the guest instruction; and
substitute corresponding bit fields in an equivalent native instruction as the bit fields are detected.
21. The microprocessor of claim 20 , wherein the first level conversion table and the second level conversion table include a control field operable to identify a next relevant bit field to be substituted in the equivalent native instruction.