Accelerated code optimizer for a multiengine microprocessor
View Patent ↗A method for accelerating code optimization a microprocessor. The method includes fetching an incoming microinstruction sequence using an instruction fetch component and transferring the fetched macroinstructions to a decoding component for decoding into microinstructions. Optimization processing is performed by reordering the microinstruction sequence into an optimized microinstruction sequence comprising a plurality of dependent code groups. The plurality of dependent code groups are then output to a plurality of engines of the microprocessor for execution in parallel. A copy of the optimized microinstruction sequence is stored into a sequence cache for subsequent use upon a subsequent hit optimized microinstruction sequence.
1. A method for accelerating code optimization in a microprocessor, comprising:
fetching an incoming macro instruction sequence using an instruction fetch component;
transferring the incoming macro instruction sequence to a decoding component for decoding into a microinstruction sequence;
performing optimization processing by reordering the microinstruction sequence into an optimized microinstruction sequence comprising a plurality of dependent code groups, wherein performing the optimization processing includes checking for true dependencies, output dependencies, and anti-dependencies in the microinstruction sequence to determine which microinstructions of the microinstruction sequence are grouped into a same dependent code group of the plurality of dependent code groups;
outputting the plurality of dependent code groups to a plurality of engines of the microprocessor for execution in parallel; and
storing a copy of the optimized microinstruction sequence into a sequence cache for subsequent use upon a subsequent hit on the optimized microinstruction sequence.
2. The method of claim 1 , wherein a copy of the decoded microinstruction sequence stored in a microinstruction cache.
3. The method of claim 1 , wherein the optimization processing is performed using an allocation and issue stage of the microprocessor.
4. The method of claim 3 , wherein the allocation and issue stage further comprises an instruction scheduling and optimizer component that reorders the microinstruction sequence into the optimized microinstruction sequence.
5. The method of claim 1 , wherein the optimization processing further comprises dynamically unrolling microinstruction sequences.
6. The method of claim 1 , wherein the optimization processing is implemented through a plurality of iterations.
7. The method of claim 1 , wherein the optimization processing is implemented through a register renaming process to enable the reordering.
8. A microprocessor, comprising:
an instruction fetch component for fetching an incoming macroinstruction sequence;
a decoding component coupled to the instruction fetch component to receive the macroinstruction sequence and decode into a microinstruction sequence;
an allocation and issue stage coupled to the decoding component to receive the microinstruction sequence and perform optimization processing by reordering the microinstruction sequence into an optimized microinstruction sequence comprising a plurality of dependent code groups, wherein performing the optimization processing includes checking for true dependencies, output dependencies, and anti-dependencies in the microinstruction sequence to determine which microinstructions of the microinstruction sequence are grouped into a same dependent code group of the plurality of dependent code groups;
a plurality of engines of the microprocessor coupled to the allocation and issue stage to receive the plurality of dependent code groups for execution in parallel; and
a sequence cache coupled to the allocation and issue stage to receive and store a copy of the optimized microinstruction sequence for subsequent use upon a subsequent hit on the optimized microinstruction sequence.
9. The microprocessor of claim 8 , wherein a copy of the decoded microinstruction sequence is stored in a microinstruction cache.
10. The microprocessor of claim 8 , wherein the optimization processing is performed using an allocation and issue stage of the microprocessor.
11. The microprocessor of claim 10 , wherein the allocation and issue stage further comprises an instruction scheduling and optimizer component that reorders the microinstruction sequence into the optimized microinstruction sequence.
12. The microprocessor of claim 8 , wherein the optimization processing further comprises dynamically unrolling microinstruction sequences.
13. The microprocessor of claim 8 , wherein the optimization processing is implemented through a plurality of iterations.
14. The microprocessor of claim 8 , wherein the optimization processing is implemented through a register renaming process to enable the reordering.