SYSTEM CONVERTER THAT EXECUTES A JUST IN TIME OPTIMIZER FOR EXECUTING CODE FROM A GUEST IMAGE

1 . A system for an agnostic runtime architecture, comprising:

a system emulation/virtualization converter;

an application code converter; and

a system converter wherein the system emulation/virtualization converter and the application code converter implement a system emulation process, and wherein the system converter implements a system conversion process for executing code from a guest image;

wherein the system converter executes a JIT optimizer, and wherein the JIT optimizer ensures loads are not dispatch ahead of other loads that are to a same memory address by checking for the same address from subsequent loads from a same thread.

2 . The system of claim 1 , wherein a reordered load instruction check will stay in a store queue after retirement up to a point of the original location of the reordered load instruction.

3 . The system of claim 1 , wherein a load check extension size is determined by putting a restriction on the number of loads that a reordered load can jump ahead of.

4 . The system of claim 1 , wherein the JIT optimizer is configured for a partial store ordering memory consistency model (e.g., ARM consistency model).

5 . The system of claim 1 , wherein the processor is further includes a sequence cache to store dynamically converted sequences.

6 . The system of claim 1 , wherein the dynamic sequence block-based instruction mapping component further comprises:

a system emulation/virtualization converter;

an application code converter; and

a system converter wherein the system emulation/virtualization converter and the application code converter implement a system emulation process, and wherein the system converter implements a system conversion process for executing code from a guest image.

7 . The system of claim 6 , wherein the system conversion process utilizes multi-pass optimization process.

8 . A microprocessor, comprising:

a system emulation/virtualization converter;

an application code converter; and

a system converter wherein the system emulation/virtualization converter and the application code converter implement a system emulation process, and wherein the system converter implements a system conversion process for executing code from a guest image;

wherein the system converter executes a JIT optimizer, and wherein the JIT optimizer ensures loads are not dispatch ahead of other loads that are to a same memory address by checking for the same address from subsequent loads from a same thread.

9 . The microprocessor of claim 8 , wherein a reordered load instruction check will stay in a store queue after retirement up to a point of the original location of the reordered load instruction.

10 . The microprocessor of claim 8 , wherein a load check extension size is determined by putting a restriction on the number of loads that a reordered load can jump ahead of.

11 . The microprocessor of claim 8 , wherein the JIT optimizer is configured for a partial store ordering memory consistency model (e.g., ARM consistency model).

12 . The microprocessor of claim 8 , wherein the processor is further includes a sequence cache to store dynamically converted sequences.

13 . The microprocessor of claim 8 , wherein the dynamic sequence block-based instruction mapping component further comprises:

a system emulation/virtualization converter;

an application code converter; and

a system converter wherein the system emulation/virtualization converter and the application code converter implement a system emulation process, and wherein the system converter implements a system conversion process for executing code from a guest image.

14 . The microprocessor of claim 13 , wherein the system conversion process utilizes multi-pass optimization process. component and the runtime native instruction sequence formation component and allocates the resulting processed instructions to a processor for execution.

15 . A computer system, comprising

a microprocessor having a core and a plurality of caches, wherein the microprocessor further comprises;

a system emulation/virtualization converter;

an application code converter; and

a system converter wherein the system emulation/virtualization converter and the application code converter implement a system emulation process, and wherein the system converter implements a system conversion process for executing code from a guest image;

wherein the system converter executes a JIT optimizer, and wherein the JIT optimizer ensures loads are not dispatch ahead of other loads that are to a same memory address by checking for the same address from subsequent loads from a same thread.

16 . The microprocessor of claim 15 , wherein a reordered load instruction check will stay in a store queue after retirement up to a point of the original location of the reordered load instruction.

17 . The microprocessor of claim 15 , wherein a load check extension size is determined by putting a restriction on the number of loads that a reordered load can jump ahead of.

18 . The microprocessor of claim 15 , wherein the JIT optimizer is configured for a partial store ordering memory consistency model (e.g., ARM consistency model).

19 . The microprocessor of claim 15 , wherein the processor is further includes a sequence cache to store dynamically converted sequences.

20 . The microprocessor of claim 15 , wherein the dynamic sequence block-based instruction mapping component further comprises:

a system emulation/virtualization converter;

an application code converter; and

a system converter wherein the system emulation/virtualization converter and the application code converter implement a system emulation process, and wherein the system converter implements a system conversion process for executing code from a guest image.