Patent Assignment
Reel/Frame 050260/0167
Assignment of Assignor's Interest
Recorded: 2019-09-04
Pages: 6
Assignors
SMITH, JEFFREY
Executed: 2019-09-03
DEVILLIERS, ANTON J.
Executed: 2019-09-03
TAPILY, KANDABARA
Executed: 2019-09-03
Assignee
TOKYO ELECTRON LIMITED
AKASAKA BIZ TOWER, 3-1 AKASAKA 5-CHOME, MINATO-KU, TOKYO, 107-6325, JAPAN
Covered Property
(1)
Method to Vertically Route a Logic Cell Incorporating Stacked Transistors in a Three Dimensional Logic Device