Method to vertically route a logic cell incorporating stacked transistors in a three dimensional logic device

1. A semiconductor device, comprising:

a substrate having a surface, the surface being planar;

a first logic gate provided on the substrate and comprising a first field effect transistor (FET) having a first channel, and a first pair of source-drain regions;

a second logic gate stacked over the first logic gate along a vertical direction perpendicular to the surface of the substrate, the second logic gate comprising a second FET having a second channel, and a second pair of source-drain regions;

a dielectric film formed between the first logic gate and the second logic gate and separating the first logic gate from the second logic gate; and

a first contact extending from a first source-drain electrode of the first FET to a second source-drain electrode of the second FET such that at least a portion of current flowing between the first and second logic gates will flow along the vertical direction,

wherein the first source-drain electrode of the first FET is partially embedded in the dielectric film and partially embedded in the first contact.

2. The semiconductor device of claim 1 , wherein

said first logic gate comprises a first set of complementary FETs including said first FET; and

said second logic gate comprises a second set of complementary FETs including said second FET.

3. The semiconductor device of claim 2 , wherein at least one of said first and second sets of complementary FETs comprises laterally arranged complementary FETS spaced from one another in a lateral direction along said surface of the substrate.

4. The semiconductor device of claim 2 , wherein at least one of said first and second sets of complementary FETs comprises stacked complementary FETS spaced along said vertical direction.

5. The semiconductor device of claim 1 , further comprising a power rail configured to provide current to said first and second logic gate, wherein said power rail comprises a back end of line (BEOL) power rail positioned over said second logic gate along said vertical direction.

6. The semiconductor device of claim 1 , further comprising a power rail configured to provide current to said first and second logic gate, wherein said power rail comprises a buried power rail positioned below said first logic gate along said vertical direction.

7. The semiconductor device of claim 1 , further comprising:

a third logic gate provided on the substrate laterally adjacent to the first logic gate and comprising a third FET having a third channel, and a third pair of source-drain regions;

a fourth logic gate stacked over the third logic gate along said vertical direction perpendicular to the surface of the substrate, the fourth logic gate comprising a fourth FET having a fourth channel, and a fourth pair of source-drain regions;

a second contact electrically connecting a third source-drain region of the third FET to a fourth source-drain region of the fourth FET such that at least a portion of current flowing between the third and fourth logic gate will flow along said vertical direction; and

a third contact electrically connecting a source-drain region of the first pair of source drain regions to a source-drain region of the third pair of source-drain regions such that at least a portion of current flowing between the first and third logic gate will flow along a lateral direction.

8. The semiconductor device of claim 1 , further comprising:

a third logic gate stacked over the second logic gate along said vertical direction, the third logic gate comprising a third FET having a third channel, and a third pair of source-drain regions; and

a second contact electrically connecting a source-drain region of the second pair of source-drain regions to a source-drain region of the third pair of source-drain regions such that at least a portion of current flowing between the second and third logic gate will flow along said vertical direction.

9. A combination logic cell comprising:

a substrate having a surface, the surface being planar;

a plurality of logic gates stacked in relation to one another along a vertical direction perpendicular to the surface of the substrate and separated from one another by a dielectric film; and

a contact extending along the vertical direction from an output of one of the plurality of logic gates to an input of the other one of the plurality of logic gates such that at least a portion of current flowing between the plurality of logic gates will flow along the vertical direction,

wherein an output source-drain electrode of a first logic gate of said plurality of logic gates or an input source-drain electrode of a second logic gate of said plurality of logic gates is partially embedded in the dielectric film and partially embedded in the contact.

10. The combinational logic cell of claim 9 , wherein said plurality of logic gates occupy a single contacted gate pitch in a first direction along said surface of the substrate.

11. The combinational logic cell of claim 10 , wherein said plurality of logic gates occupy more than one critical metal pitch in a second direction along said surface of the substrate and non-parallel to said first direction.

12. The combinational logic cell of claim 10 , wherein

said plurality of logic gates comprises three logic gates stacked in relation to one another along said vertical direction; and

said contact comprises a plurality of contacts configured to electrically interconnect said plurality of logic gates in a configuration of an AND-OR-Invert (AOI) cell.

13. A semiconductor device, comprising:

a substrate;

a first field effect transistor (FET) provided on the substrate in a first deck and including a first channel, a first gate structure, a first source electrode, and a first drain electrode;

a second FET stacked vertically perpendicular to a plane of the substrate on top of the first FET in a second deck, and including a first channel, a first gate structure, a first source electrode, and a first drain electrode;

a dielectric film formed between the first FET and the second FET and separating the first FET from the second FET;

a contact extending from the first source electrode of the first FET to the first source electrode of the second FET or connecting the first drain electrode of the first FET to the first drain electrode of the second FET such that at least a portion of current flowing between the first FET and the second FET will flow along the vertical direction; and

a current source electrically connected to the first source electrode or first drain electrode of the first FET, wherein

current provided by the current source flows through the first FET in the first deck,

current exiting the first source electrode of the first FET or first drain electrode of the first FET flows vertically upwards to the second deck into the first source electrode of the second FET or the first drain electrode of the second FET,

and

at least one of the first source electrode and the first drain electrode of the first FET and the first source electrode and the first drain electrode of the second FET is partially embedded in the dielectric film and partially embedded in the contact.

14. The device of claim 13 further comprising additional FETs, each additional FET being stacked overtop one another in additional decks.

15. The device of claim 13 , wherein

the first FET is part of a first complementary FET (CFET) and the second FET is part of a second CFET;

the first CFET includes a second channel, a second gate structure, a second source electrode, and a second drain electrode;

the second CFET includes a second channel, a second gate structure, a second source electrode, and a second drain electrode;

a first channel of the first CFET provides an NMOS channel and the second channel of the first CFET provides a PMOS channel;

a first channel of the second CFET provides an NMOS channel and the second channel of the second CFET provides a PMOS channel.

16. The device of claim 15 , wherein

the second channel of the first CFET is disposed laterally adjacent to the first channel of the first CFET; and

the second channel of the second CFET is disposed laterally adjacent to the first channel of the second CFET.

17. The device of claim 15 , wherein

the second channel of the first CFET is disposed vertically over top the first channel of the first CFET; and

the second channel of the second CFET is disposed vertically over top the first channel of the second CFET.

18. The device of claim 17 , wherein:

said second gate structure is stacked vertically perpendicular to the plane of the substrate over top the first gate structure, and

said first and second gate structures include respective gate electrodes which are staggered in relation to one another in a lateral direction along said plane of the substrate.

19. The semiconductor device of claim 1 , wherein the second source-drain electrode of the second FET is partially embedded in the dielectric film and partially embedded in the first contact.

20. The combination logic cell of claim 9 , wherein both the output source-drain electrode of the first logic gate and the input source-drain electrode of the second logic gate are partially embedded in the dielectric film and partially embedded in the contact.