IP Library › Assignment 050744/0671
Patent Assignment
Reel/Frame 050744/0671

ASSIGNMENT OF ASSIGNOR'S INTEREST

Recorded: 2019-10-17 Received: 2019-10-17 Pages: 2
Assignors
BURGESS, IAN
Executed: 2019-10-08
MARSHALL, DUANE
Executed: 2019-10-08
Assignee
ACUSHNET COMPANY
333 BRIDGE STREET, P. O. BOX 965, FAIRHAVEN, MA, 02719-0965, UNITED STATES
Covered Applications (92)
GOLF BAG
App. No. 29/709,775
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APPARATUS AND METHOD FOR CONTROLLING CHARGE PUMP
App. No. 14/165,598
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SYSTEM FOR OPTIMIZING NUMBER OF DIES PRODUCED ON A WAFER
App. No. 13/723,207
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SEMICONDUCTOR PACKAGE SIGNAL ROUTING USING CONDUCTIVE VIAS
App. No. 13/718,081
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REDUCING MEMS STICTION BY DEPOSITION OF NANOCLUSTERS
App. No. 13/718,614
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REDUCING MEMS STICTION BY INTRODUCTION OF A CARBON BARRIER
App. No. 13/718,598
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MULTI-VOLTAGE DOMAIN CIRCUIT DESIGN VERIFICATION METHOD
App. No. 13/717,646
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RAIL TO RAIL DIFFERENTIAL BUFFER INPUT STAGE
App. No. 13/716,194
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BAND GAP REFERENCE VOLTAGE GENERATOR
App. No. 13/714,415
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INTEGRATED CIRCUITS INCLUDING INTEGRATED PASSIVE DEVICES AND METHODS OF MANUFACTURE THEREOF
App. No. 13/712,051
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SYSTEMS WITH ADJUSTABLE SAMPLING PARAMETERS AND METHODS OF THEIR OPERATION
App. No. 13/712,070
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REDUCING THE POWER CONSUMPTION OF MEMORY DEVICES
App. No. 13/709,103
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RANDOM ACCESS OF A CACHE PORTION USING AN ACCESS MODULE
App. No. 13/690,888
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AC COUPLED LEVEL SHIFTER
App. No. 13/690,336
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OVER VOLTAGE PROTECTION FOR A THIN OXIDE LOAD CIRCUIT
App. No. 13/690,046
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INTEGRATED CIRCUIT DEVICE, ELECTRONIC DEVICE AND METHOD FOR DETECTING TIMING VIOLATIONS WITHIN A CLOCK SIGNAL
App. No. 13/701,303
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ELECTRONIC DEVICES WITH EMBEDDED DIE INTERCONNECT STRUCTURES, AND METHODS OF MANUFACTURE THEREOF
App. No. 13/688,820
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SEMICONDUCTOR DEVICE PACKAGE
App. No. 13/689,034
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SYSTEMS AND METHODS FOR CONTROLLING POWER IN SEMICONDUCTOR CIRCUITS
App. No. 13/689,043
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METHODS FOR THE FABRICATION OF SEMICONDUCTOR DEVICES INCLUDING SUB-ISOLATION BURIED LAYERS
App. No. 13/689,274
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SYSTEMS AND METHODS FOR DELIVERING POWER IN RESPONSE TO A CONNECTION EVENT
App. No. 13/689,037
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PROVIDING AN AUTOMATIC OPTICAL INSPECTION FEATURE FOR SOLDER JOINTS ON SEMICONDUCTOR PACKAGES
App. No. 13/689,424
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MEMORY COLUMN DROWSY CONTROL
App. No. 13/689,331
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INERTIAL SENSOR AND METHOD OF LEVITATION EFFECT COMPENSATION
App. No. 13/687,299
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SPRING FOR MICROELECTROMECHANICAL SYSTEMS (MEMS) DEVICE
App. No. 13/687,424
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VOLTAGE RAMP-UP PROTECTION
App. No. 13/686,889
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METHOD AND INTEGRATED CIRCUIT THAT PROVIDES TRACKING BETWEEN MULTIPLE REGULATED VOLTAGES
App. No. 13/686,901
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ELECTRONIC DEVICES WITH CAVITY-TYPE, PERMEABLE MATERIAL FILLED PACKAGES, AND METHODS OF THEIR MANUFACTURE
App. No. 13/686,102
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TEST STRUCTURE ACTIVATED BY PROBE NEEDLE
App. No. 13/684,840
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LOW POWER SCAN FLIP-FLOP CELL
App. No. 13/682,749
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SYSTEM FOR DATA TRANSFER BETWEEN ASYNCHRONOUS CLOCK DOMAINS
App. No. 13/682,755
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FLEXIBLE CONTROL MECHANISM FOR STORE GATHERING IN A WRITE BUFFER
App. No. 13/682,350
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LOW-POWER VOLTAGE TAMPER DETECTION
App. No. 13/681,956
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INTEGRATED CIRCUIT ELECTRICAL PROTECTION DEVICE
App. No. 13/682,558
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FLEXIBLE CONTROL MECHANISM FOR STORE GATHERING IN A WRITE BUFFER
App. No. 13/682,367
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TRIGGER CIRCUIT AND METHOD FOR IMPROVED TRANSIENT IMMUNITY
App. No. 13/682,604
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SEMICONDUCTOR DEVICE PACKAGE WITH CAP ELEMENT
App. No. 13/681,437
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SYSTEM AND METHOD FOR PERFORMING SCAN TEST
App. No. 13/681,406
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DYNAMIC READ SCHEME FOR HIGH RELIABILITY HIGH PERFORMANCE FLASH MEMORY
App. No. 13/679,481
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NON-VOLATILE MEMORY ROBUST START-UP USING ANALOG-TO-DIGITAL CONVERTER
App. No. 13/679,515
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TABLE MODEL CIRCUIT SIMULATION ACCELERATION USING MODEL CACHING
App. No. 13/678,789
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POWER SWITCHING APPARATUS AND METHOD FOR IMPROVING CURRENT SENSE ACCURACY
App. No. 13/698,122
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INTEGRATED CIRCUIT WITH DEGRADATION MONITORING
App. No. 13/677,800
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TEMPERATURE DEPENDENT TIMER CIRCUIT
App. No. 13/678,117
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TRACE ROUTING WITHIN A SEMICONDUCTOR PACKAGE SUBSTRATE
App. No. 13/675,008
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PROGRAMMING A NON-VOLATILE MEMORY (NVM) SYSTEM HAVING ERROR CORRECTION CODE (ECC)
App. No. 13/674,367
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WETTABLE LEAD ENDS ON A FLAT-PACK NO-LEAD MICROELECTRONIC PACKAGE
App. No. 13/673,212
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OFFSET ERROR AUTOMATIC CALIBRATION INTEGRATED CIRCUIT
App. No. 13/671,951
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PROTECTION DEVICE AND RELATED FABRICATION METHODS
App. No. 13/671,623
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SEMICONDUCTOR DEVICE AND DRIVER CIRCUIT WITH AN ACTIVE DEVICE AND ISOLATION STRUCTURE INTERCONNECTED THROUGH A RESISTOR CIRCUIT, AND METHOD OF MANUFACTURE THEREOF
App. No. 13/671,506
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SEMICONDUCTOR DEVICE AND DRIVER CIRCUIT WITH AN ACTIVE DEVICE AND ISOLATION STRUCTURE INTERCONNECTED THROUGH A DIODE CIRCUIT, AND METHOD OF MANUFACTURE THEREOF
App. No. 13/671,503
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DELAY COMPENSATED CONTINUOUS TIME SIGMA DELTA ANALOG-TO-DIGITAL CONVERTER
App. No. 13/668,496
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HARDWARE-BASED MEMORY INITIALIZATION
App. No. 13/668,951
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Vector NCO and Twiddle Factor Generator
App. No. 13/666,289
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INTEGRATED CIRCUIT, ELECTRONIC DEVICE AND ESD PROTECTION THEREFOR
App. No. 13/695,670
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RELAXATION OSCILLATOR
App. No. 13/665,903
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SYSTEM FOR GENERATING GATED CLOCK SIGNALS
App. No. 13/665,921
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METHODS AND INTEGRATED CIRCUIT PACKAGE FOR SENSING FLUID PROPERTIES
App. No. 13/665,840
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MEMORY DEVICE REDUNDANCY MANAGEMENT SYSTEM
App. No. 13/665,917
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METHOD AND APPARATUS FOR A TUNABLE DRIVER CIRCUIT
App. No. 13/665,864
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GATE DRIVER WITH DESATURATION DETECTION AND ACTIVE CLAMPING
App. No. 13/665,518
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LDMOS Device with Minority Carrier Shunt Region
App. No. 13/665,665
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SYSTEMS AND METHODS FOR DETERMINING AGING DAMAGE FOR SEMICONDUCTOR DEVICES
App. No. 13/665,256
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SYSTEM AND METHOD FOR ASSIGNING A MESSAGE
App. No. 13/664,565
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SENSOR SINGLE TRACK TRIM USING STATIONARY HARDWARE AND FIELDS
App. No. 13/663,998
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PRODUCTION-TEST DIE TEMPERATURE MEASUREMENT
App. No. 13/663,991
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CONTROL GATE WORD LINE DRIVER CIRCUIT FOR MULTIGATE MEMORY
App. No. 13/663,636
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SEMICONDUCTOR DEVICE WITH THERMAL DISSIPATION LEAD FRAME
App. No. 13/663,462
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METHOD OF MAKING A LOGIC TRANSISTOR AND A NON-VOLATILE MEMORY (NVM) CELL
App. No. 13/661,157
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METHODS AND STRUCTURES FOR CAPPING A STRUCTURE WITH A PROTECTIVE COATING
App. No. 13/661,377
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SRAM WITH IMPROVED WRITE OPERATION
App. No. 13/661,861
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VIA PLACEMENT AND ELECTRONIC CIRCUIT DESIGN PROCESSING METHOD AND ELECTRONIC CIRCUIT DESIGN UTILIZING SAME
App. No. 13/661,131
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INTEGRATED CIRCUIT DEVICE, SIGNAL PROCESSING SYSTEM AND METHOD FOR MANAGING POWER RESOURCES OF A SIGNAL PROCESSING SYSTEM
App. No. 13/643,358
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PACKAGED INTEGRATED CIRCUIT HAVING LARGE SOLDER PADS AND METHOD FOR FORMING
App. No. 13/660,243
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PACKAGING FOR SEMICONDUCTOR SENSOR DEVICES AND METHODS
App. No. 13/657,250
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HIGH VOLTAGE DIODE
App. No. 13/656,122
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DYNAMICALLY BIASED OUTPUT STRUCTURE
App. No. 13/656,253
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AMPLIFIER CALIBRATION
App. No. 13/656,551
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FLEXIBLE CONTROL MECHANISM FOR STORE GATHERING IN A WRITE BUFFER
App. No. 13/656,073
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RESURF HIGH VOLTAGE DIODE
App. No. 13/656,103
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ELECTRONIC CIRCUITS WITH VARIABLE ATTENUATORS AND METHODS OF THEIR OPERATION
App. No. 13/653,155
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PROCESSOR SWITCHABLE BETWEEN TEST AND DEBUG MODES
App. No. 13/650,141
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TIMING EVENT GENERATION CIRCUIT FOR MOBILE COMMUNICATION DEVICE
App. No. 13/650,138
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CHIP-LEVEL HUMIDITY PROTECTION
App. No. 13/650,872
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Method and System for Low Power Transmission and Data Alignment
App. No. 13/649,461
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COMPILER OPTIMIZED SAFETY MECHANISM
App. No. 13/648,501
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LATENT SLOW BIT DETECTION FOR NON-VOLATILE MEMORY
App. No. 13/647,951
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OPPORTUNISTIC CACHE REPLACEMENT POLICY
App. No. 13/645,050
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Method and System for Automatically Controlling the Insertion of Control Word in CPRI Daisy Chain Configuration
App. No. 13/632,549
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Multiply and Accumulate Feedback
App. No. 13/632,616
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SPLIT GATE FLASH CELL
App. No. 13/633,124
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VIDEO DE-INTERLACER USING MOTION RESIDUE COMPENSATION
App. No. 11/670,846
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