Assignment of Assignor's Interest

Recorded: 2020-01-08 Pages: 7

Assignors

DING, YI-XIAO

Executed: 2019-12-27

GAO, JHIH-RONG

Executed: 2020-01-01

LI, ZHUO

Executed: 2020-01-03

Assignee

CADENCE DESIGN SYSTEMS, INC.

2655 SEELY AVENUE, SAN JOSE, CALIFORNIA, 95134

Covered Property (1)

Buffer Insertion Technique to Consider Edge Spacing and Stack via Design Rules

Patent: 10,963,620 →

Application: 16/735,662 →