Patent Assignment
Reel/Frame 051803/0664
Assignment of Assignor's Interest
Recorded: 2020-02-12
Pages: 10
Assignors
HUH, IN
Executed: 2019-06-18
KO, JEONG-HOON
Executed: 2019-06-18
CHOI, HYO-JIN
Executed: 2019-06-18
KIM, SEUNG-JU
Executed: 2019-06-18
JEONG, CHANG-WOOK
Executed: 2019-06-20
CHAI, JOON-WAN
Executed: 2019-06-19
PARK, KWANG-IL
Executed: 2019-06-20
PARK, YOUN-SIK
Executed: 2019-06-18
PARK, HYUN-SUN
Executed: 2019-06-24
OH, YOUNG-MIN
Executed: 2019-06-24
LEE, JUN-HAENG
Executed: 2019-06-24
LEE, TAE-HO
Executed: 2020-02-10
Assignee
SAMSUNG ELECTRONICS CO., LTD.
129, SAMSUNG-RO, YEONGTONG-GU, GYEONGGI-DO, SUWON-SI, 16677, KOREA, REPUBLIC OF
Covered Property
(1)
Device for Generating Verification Vector for Circuit Design Verification, Circuit Design System, and Reinforcement Learning Method of the Device and the Circuit Design System